1 /* $NetBSD: if_cs_mainbus.c,v 1.2 2007/10/17 19:54:19 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_cs_mainbus.c,v 1.2 2007/10/17 19:54:19 garbled Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/systm.h> 45 #include <sys/socket.h> 46 47 #include "rnd.h" 48 #if NRND > 0 49 #include <sys/rnd.h> 50 #endif 51 52 #include <net/if.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/if_inarp.h> 58 #endif 59 60 #include <machine/bus.h> 61 #include <machine/pio.h> 62 #include <machine/pmppc.h> 63 #include <arch/evbppc/pmppc/dev/mainbus.h> 64 65 #include <dev/ic/cs89x0reg.h> 66 #include <dev/ic/cs89x0var.h> 67 68 #include <sys/callout.h> 69 70 #define ATSN_EEPROM_MAC_OFFSET 0x20 71 72 73 static void cs_check_eeprom(struct cs_softc *sc); 74 75 static int cs_mainbus_match(struct device *, struct cfdata *, void *); 76 static void cs_mainbus_attach(struct device *, struct device *, void *); 77 78 CFATTACH_DECL(cs_mainbus, sizeof(struct cs_softc), 79 cs_mainbus_match, cs_mainbus_attach, NULL, NULL); 80 81 int 82 cs_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 83 { 84 struct mainbus_attach_args *maa = aux; 85 86 return (strcmp(maa->mb_name, "cs") == 0); 87 } 88 89 #if 0 90 static u_int64_t 91 in64(uint a) 92 { 93 union { 94 double d; 95 u_int64_t i; 96 } u; 97 double save, *dp = (double *)a; 98 u_int32_t msr, nmsr; 99 100 __asm volatile("mfmsr %0" : "=r"(msr)); 101 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 102 __asm volatile("mtmsr %0" :: "r"(nmsr)); 103 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 104 __asm volatile( 105 "stfd 0,%0\n\ 106 lfd 0,%1\n\ 107 stfd 0,%2\n\ 108 lfd 0,%0" 109 : "=m"(save), "=m"(*dp) 110 : "m"(u.d) 111 ); 112 __asm volatile ("eieio; sync"); 113 __asm volatile("mtmsr %0" :: "r"(msr)); 114 return (u.i); 115 } 116 #endif 117 118 static void 119 out64(uint a, u_int64_t v) 120 { 121 union { 122 double d; 123 u_int64_t i; 124 } u; 125 double save, *dp = (double *)a; 126 u_int32_t msr, nmsr; 127 int s; 128 129 s = splhigh(); 130 u.i = v; 131 __asm volatile("mfmsr %0" : "=r"(msr)); 132 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 133 __asm volatile("mtmsr %0" :: "r"(nmsr)); 134 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 135 __asm volatile( 136 "stfd 0,%0\n\ 137 lfd 0,%2\n\ 138 stfd 0,%1\n\ 139 lfd 0,%0" 140 : "=m"(save), "=m"(*dp) 141 : "m"(u.d) 142 ); 143 __asm volatile ("eieio; sync"); 144 __asm volatile("mtmsr %0" :: "r"(msr)); 145 splx(s); 146 } 147 148 static u_int8_t 149 cs_io_read_1(struct cs_softc *sc, bus_size_t offs) 150 { 151 u_int32_t a, v; 152 153 a = sc->sc_ioh + (offs << 2); 154 v = in8(a); 155 return v; 156 } 157 158 static u_int16_t 159 cs_io_read_2(struct cs_softc *sc, bus_size_t offs) 160 { 161 u_int32_t a, v; 162 163 a = sc->sc_ioh + (offs << 2); 164 v = in16(a); 165 return v; 166 } 167 168 static void 169 cs_io_read_multi_2(struct cs_softc *sc, bus_size_t offs, u_int16_t *buf, 170 bus_size_t cnt) 171 { 172 u_int32_t a, v; 173 174 a = sc->sc_ioh + (offs << 2); 175 while (cnt--) { 176 v = in16(a); 177 *buf++ = bswap16(v); 178 } 179 } 180 181 static void 182 cs_io_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data) 183 { 184 u_int32_t a; 185 u_int64_t v; 186 187 a = sc->sc_ioh + (offs << 2); 188 v = (u_int64_t)data << 48; 189 out64(a, v); 190 191 (void)in16(a); /* CPC700 write post bug */ 192 } 193 194 static void 195 cs_io_write_multi_2(struct cs_softc *sc, bus_size_t offs, 196 const u_int16_t *buf, bus_size_t cnt) 197 { 198 u_int16_t v; 199 double save, *dp; 200 union { 201 double d; 202 u_int64_t i; 203 } u; 204 u_int32_t msr, nmsr; 205 int s; 206 207 dp = (double *)(sc->sc_ioh + (offs << 2)); 208 209 s = splhigh(); 210 __asm volatile("mfmsr %0" : "=r"(msr)); 211 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 212 __asm volatile("mtmsr %0" :: "r"(nmsr)); 213 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 214 __asm volatile("stfd 0,%0" : "=m"(save)); 215 216 while (cnt--) { 217 v = *buf++; 218 v = bswap16(v); 219 u.i = (u_int64_t)v << 48; 220 __asm volatile("lfd 0,%1\nstfd 0,%0" : "=m"(*dp) : "m"(u.d) ); 221 __asm volatile ("eieio; sync"); 222 } 223 __asm volatile("lfd 0,%0" :: "m"(save)); 224 __asm volatile("mtmsr %0" :: "r"(msr)); 225 splx(s); 226 } 227 228 static u_int16_t 229 cs_mem_read_2(struct cs_softc *sc, bus_size_t offs) 230 { 231 panic("cs_mem_read_2"); 232 } 233 234 static void 235 cs_mem_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data) 236 { 237 panic("cs_mem_write_2"); 238 } 239 240 static void 241 cs_mem_write_region_2(struct cs_softc *sc, bus_size_t offs, 242 const u_int16_t *buf, bus_size_t cnt) 243 { 244 panic("cs_mem_write_region_2"); 245 } 246 247 void 248 cs_mainbus_attach(struct device *parent, struct device *self, void *aux) 249 { 250 struct cs_softc *sc = (struct cs_softc *)self; 251 struct mainbus_attach_args *maa = aux; 252 int media[1] = { IFM_ETHER | IFM_10_T }; 253 254 printf("\n"); 255 256 sc->sc_iot = maa->mb_bt; 257 sc->sc_memt = maa->mb_bt; 258 sc->sc_irq = maa->mb_irq; 259 260 if (bus_space_map(sc->sc_iot, PMPPC_CS_IO, CS8900_IOSIZE*4, 261 0, &sc->sc_ioh)) { 262 printf("%s: failed to map io\n", self->dv_xname); 263 return; 264 } 265 266 cs_check_eeprom(sc); 267 268 sc->sc_ih = intr_establish(sc->sc_irq, IST_LEVEL, IPL_NET, cs_intr, sc); 269 if (!sc->sc_ih) { 270 printf("%s: unable to establish interrupt\n", 271 self->dv_xname); 272 goto fail; 273 } 274 275 sc->sc_cfgflags = CFGFLG_NOT_EEPROM; 276 277 sc->sc_io_read_1 = cs_io_read_1; 278 sc->sc_io_read_2 = cs_io_read_2; 279 sc->sc_io_read_multi_2 = cs_io_read_multi_2; 280 sc->sc_io_write_2 = cs_io_write_2; 281 sc->sc_io_write_multi_2 = cs_io_write_multi_2; 282 sc->sc_mem_read_2 = cs_mem_read_2; 283 sc->sc_mem_write_2 = cs_mem_write_2; 284 sc->sc_mem_write_region_2 = cs_mem_write_region_2; 285 286 /* 287 * We need interrupt on INTRQ0 from the CS8900 (that's what wired 288 * to the UIC). The MI driver subtracts 10 from the irq, so 289 * use 10 as the irq. 290 */ 291 sc->sc_irq = 10; 292 293 /* Use half duplex 10baseT. */ 294 if (cs_attach(sc, NULL, media, 1, IFM_ETHER | IFM_10_T)) { 295 printf("%s: unable to attach\n", self->dv_xname); 296 goto fail; 297 } 298 299 return; 300 301 fail: 302 /* XXX disestablish, unmap */ 303 return; 304 } 305 306 307 /* 308 * EEPROM initialization code. 309 */ 310 311 static uint16_t default_eeprom_cfg[] = 312 { 0xA100, 0x2020, 0x0300, 0x0000, 0x0000, 313 0x102C, 0x1000, 0x0008, 0x2158, 0x0000, 314 0x0000, 0x0000 }; 315 316 static uint16_t 317 cs_readreg(struct cs_softc *sc, uint pp_offset) 318 { 319 cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset); 320 (void)cs_io_read_2(sc, PORT_PKTPG_PTR); 321 return (cs_io_read_2(sc, PORT_PKTPG_DATA)); 322 } 323 324 static void 325 cs_writereg(struct cs_softc *sc, uint pp_offset, uint16_t value) 326 { 327 cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset); 328 (void)cs_io_read_2(sc, PORT_PKTPG_PTR); 329 cs_io_write_2(sc, PORT_PKTPG_DATA, value); 330 (void)cs_io_read_2(sc, PORT_PKTPG_DATA); 331 } 332 333 static int 334 cs_wait_eeprom_ready(struct cs_softc *sc) 335 { 336 int ms; 337 338 /* 339 * Check to see if the EEPROM is ready, a timeout is used - 340 * just in case EEPROM is ready when SI_BUSY in the 341 * PP_SelfST is clear. 342 */ 343 ms = 0; 344 while(cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY) { 345 delay(1000); 346 if (ms++ > 20) 347 return 0; 348 } 349 return 1; 350 } 351 352 static void 353 cs_wr_eeprom(struct cs_softc *sc, uint16_t offset, uint16_t data) 354 { 355 356 /* Check to make sure EEPROM is ready. */ 357 if (!cs_wait_eeprom_ready(sc)) { 358 printf("%s: write EEPROM not ready\n", sc->sc_dev.dv_xname); 359 return; 360 } 361 362 /* Enable writing. */ 363 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_ENABLE); 364 365 /* Wait for WRITE_ENABLE command to complete. */ 366 if (!cs_wait_eeprom_ready(sc)) { 367 printf("%s: EEPROM WRITE_ENABLE timeout", sc->sc_dev.dv_xname); 368 } else { 369 /* Write data into EEPROM_DATA register. */ 370 cs_writereg(sc, PKTPG_EEPROM_DATA, data); 371 delay(1000); 372 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_WRITE | offset); 373 374 /* Wait for WRITE_REGISTER command to complete. */ 375 if (!cs_wait_eeprom_ready(sc)) { 376 printf("%s: EEPROM WRITE_REGISTER timeout\n", 377 sc->sc_dev.dv_xname); 378 } 379 } 380 381 /* Disable writing. */ 382 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_DISABLE); 383 384 /* Wait for WRITE_DISABLE command to complete. */ 385 if (!cs_wait_eeprom_ready(sc)) { 386 printf("%s: WRITE_DISABLE timeout\n", sc->sc_dev.dv_xname); 387 } 388 } 389 390 static uint16_t 391 cs_rd_eeprom(struct cs_softc *sc, uint16_t offset) 392 { 393 394 if (!cs_wait_eeprom_ready(sc)) { 395 printf("%s: read EEPROM not ready\n", sc->sc_dev.dv_xname); 396 return 0; 397 } 398 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_READ | offset); 399 400 if (!cs_wait_eeprom_ready(sc)) { 401 printf("%s: EEPROM_READ timeout\n", sc->sc_dev.dv_xname); 402 return 0; 403 } 404 return cs_readreg(sc, PKTPG_EEPROM_DATA); 405 } 406 407 static void 408 cs_check_eeprom(struct cs_softc *sc) 409 { 410 uint8_t checksum; 411 int i; 412 uint16_t tmp; 413 414 /* 415 * If the SELFST[EEPROMOK] is set, then assume EEPROM configuration 416 * is valid. 417 */ 418 if (cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_EEP_OK) { 419 printf("%s: EEPROM OK, skipping initialization\n", 420 sc->sc_dev.dv_xname); 421 return; 422 } 423 printf("%s: updating EEPROM\n", sc->sc_dev.dv_xname); 424 425 /* 426 * Calculate the size (in bytes) of the default config array and write 427 * it to the lower byte of the array itself. 428 */ 429 default_eeprom_cfg[0] |= sizeof(default_eeprom_cfg); 430 431 /* 432 * Read the MAC address from its Artesyn-specified offset in the EEPROM. 433 */ 434 for (i = 0; i < 3; i++) { 435 tmp = cs_rd_eeprom(sc, ATSN_EEPROM_MAC_OFFSET + i); 436 default_eeprom_cfg[EEPROM_MAC + i] = bswap16(tmp); 437 } 438 439 /* 440 * Program the EEPROM with our default configuration, 441 * calculating checksum as we proceed. 442 */ 443 checksum = 0; 444 for (i = 0; i < sizeof(default_eeprom_cfg)/2 ; i++) { 445 tmp = default_eeprom_cfg[i]; 446 cs_wr_eeprom(sc, i, tmp); 447 checksum += tmp >> 8; 448 checksum += tmp & 0xff; 449 } 450 451 /* 452 * The CS8900a datasheet calls for the two's complement of the checksum 453 * to be prgrammed in the most significant byte of the last word of the 454 * header. 455 */ 456 checksum = ~checksum + 1; 457 cs_wr_eeprom(sc, i++, checksum << 8); 458 /* write "end of data" flag */ 459 cs_wr_eeprom(sc, i, 0xffff); 460 } 461