1 /* $NetBSD: machdep.c,v 1.2 2011/01/18 01:10:25 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetSBD$"); 40 41 #include "opt_mpc85xx.h" 42 #include "opt_altivec.h" 43 #include "opt_pci.h" 44 #include "opt_ddb.h" 45 #include "gpio.h" 46 #include "pci.h" 47 48 #define DDRC_PRIVATE 49 #define GLOBAL_PRIVATE 50 #define L2CACHE_PRIVATE 51 #define _POWERPC_BUS_DMA_PRIVATE 52 53 #include <sys/param.h> 54 #include <sys/cpu.h> 55 #include <sys/intr.h> 56 #include <sys/msgbuf.h> 57 #include <sys/tty.h> 58 #include <sys/kcore.h> 59 #include <sys/bitops.h> 60 #include <sys/bus.h> 61 #include <sys/extent.h> 62 #include <sys/malloc.h> 63 64 #include <uvm/uvm_extern.h> 65 66 #include <prop/proplib.h> 67 68 #include <machine/stdarg.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <powerpc/pcb.h> 80 #include <powerpc/spr.h> 81 #include <powerpc/booke/spr.h> 82 83 #include <powerpc/booke/cpuvar.h> 84 #include <powerpc/booke/e500reg.h> 85 #include <powerpc/booke/e500var.h> 86 #include <powerpc/booke/etsecreg.h> 87 #include <powerpc/booke/openpicreg.h> 88 #ifdef CADMUS 89 #include <evbppc/mpc85xx/cadmusreg.h> 90 #endif 91 #ifdef PIXIS 92 #include <evbppc/mpc85xx/pixisreg.h> 93 #endif 94 95 void initppc(vaddr_t, vaddr_t); 96 97 #define MEMREGIONS 4 98 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 99 phys_ram_seg_t availmemr[MEMREGIONS]; /* Available memory */ 100 static u_int nmemr; 101 102 #ifndef CONSFREQ 103 # define CONSFREQ -1 /* inherit from firmware */ 104 #endif 105 #ifndef CONSPEED 106 # define CONSPEED 115200 107 #endif 108 #ifndef CONMODE 109 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 110 #endif 111 #ifndef CONSADDR 112 # define CONSADDR DUART2_BASE 113 #endif 114 115 int comcnfreq = CONSFREQ; 116 int comcnspeed = CONSPEED; 117 tcflag_t comcnmode = CONMODE; 118 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 119 120 #if NPCI > 0 121 struct extent *pcimem_ex; 122 struct extent *pciio_ex; 123 #endif 124 125 struct powerpc_bus_space gur_bst = { 126 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 127 .pbs_offset = GUR_BASE, 128 .pbs_limit = GUR_SIZE, 129 }; 130 131 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 132 133 #ifdef CADMUS 134 static uint8_t cadmus_pci; 135 static uint8_t cadmus_csr; 136 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 137 #elif defined(PIXIS) 138 static const uint32_t pixis_spd_map[8] = { 139 [PX_SPD_33MHZ] = 33333333, 140 [PX_SPD_40MHZ] = 40000000, 141 [PX_SPD_50MHZ] = 50000000, 142 [PX_SPD_66MHZ] = 66666666, 143 [PX_SPD_83MHZ] = 83333333, 144 [PX_SPD_133MHZ] = 100000000, 145 [PX_SPD_133MHZ] = 133333333, 146 [PX_SPD_166MHZ] = 166666667, 147 }; 148 static uint8_t pixis_spd; 149 static uint64_t e500_sys_clk; 150 #elif defined(SYS_CLK) 151 static uint64_t e500_sys_clk = SYS_CLK; 152 #else 153 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 154 #endif 155 156 static int e500_cngetc(dev_t); 157 static void e500_cnputc(dev_t, int); 158 159 static struct consdev e500_earlycons = { 160 .cn_getc = e500_cngetc, 161 .cn_putc = e500_cnputc, 162 .cn_pollc = nullcnpollc, 163 }; 164 165 /* 166 * List of port-specific devices to attach to the processor local bus. 167 */ 168 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 169 { "cpu" }, /* not a real device */ 170 { "wdog" }, /* not a real device */ 171 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 1, 172 { ISOURCE_DUART }, 173 1 + ilog2(DEVDISR_DUART) }, 174 #if defined(MPC8548) || defined(MPC8572) 175 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 176 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 177 1 + ilog2(DEVDISR_TSEC1) }, 178 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 3, 179 { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 180 1 + ilog2(DEVDISR_TSEC2) }, 181 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 3, 182 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 183 1 + ilog2(DEVDISR_TSEC3) }, 184 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 3, 185 { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 186 1 + ilog2(DEVDISR_TSEC4) }, 187 #endif 188 #if defined(MPC8544) || defined(MPC8536) 189 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 3, 190 { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 191 1 + ilog2(DEVDISR_TSEC1) }, 192 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 3, 193 { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 194 1 + ilog2(DEVDISR_TSEC2) }, 195 #endif 196 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 1, 197 { ISOURCE_I2C }, 198 1 + ilog2(DEVDISR_TSEC2) }, 199 #ifndef MPC8572 200 /* MPC8572 doesn't have any GPIO */ 201 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 0 }, 202 #endif 203 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 1, 204 { ISOURCE_DDR }, 205 1 + ilog2(DEVDISR_TSEC2) }, 206 #if defined(MPC8544) || defined(MPC8536) 207 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 1, 208 { ISOURCE_PCIEX }, 209 1 + ilog2(DEVDISR_PCIE) }, 210 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 1, 211 { ISOURCE_PCIEX2 }, 212 1 + ilog2(DEVDISR_PCIE3) }, 213 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 1, 214 { ISOURCE_PCIEX3 }, 215 1 + ilog2(DEVDISR_PCIE2) }, 216 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 1, 1, 217 { ISOURCE_PCI1 }, 218 1 + ilog2(DEVDISR_PCI1) }, 219 #endif 220 #ifdef MPC8548 221 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 1, 222 { ISOURCE_PCIEX }, 223 1 + ilog2(DEVDISR_PCIE) }, 224 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 1, 225 { ISOURCE_PCI1 }, 226 1 + ilog2(DEVDISR_PCI1) }, 227 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 1, 228 { ISOURCE_PCI2 }, 229 1 + ilog2(DEVDISR_PCI2) }, 230 #endif 231 #ifdef MPC8536 232 { "ehci", USB1_BASE, USB_SIZE, 1, 1, 233 { ISOURCE_USB1 }, 234 1 + ilog2(DEVDISR_USB1) }, 235 { "ehci", USB2_BASE, USB_SIZE, 2, 1, 236 { ISOURCE_USB2 }, 237 1 + ilog2(DEVDISR_USB2) }, 238 { "ehci", USB3_BASE, USB_SIZE, 3, 1, 239 { ISOURCE_USB3 }, 240 1 + ilog2(DEVDISR_USB3) }, 241 { "sata", SATA1_BASE, SATA_SIZE, 1, 1, 242 { ISOURCE_SATA1 }, 243 1 + ilog2(DEVDISR_SATA1) }, 244 { "sata", SATA2_BASE, SATA_SIZE, 2, 1, 245 { ISOURCE_SATA2 }, 246 1 + ilog2(DEVDISR_SATA2) }, 247 { "spi", SPI_BASE, SPI_SIZE, 0, 1, 248 { ISOURCE_SPI }, 249 1 + ilog2(DEVDISR_SPI) }, 250 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 1, 251 { ISOURCE_ESDHC }, 252 1 + ilog2(DEVDISR_ESDHC) }, 253 #endif 254 { "lbc", LBC_BASE, LBC_SIZE, 0, 1, 255 { ISOURCE_LBC }, 256 1 + ilog2(DEVDISR_LBC) }, 257 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 258 { NULL } 259 }; 260 261 static int 262 e500_cngetc(dev_t dv) 263 { 264 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 265 266 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 267 return -1; 268 269 return com0addr[com_data] & 0xff; 270 } 271 272 static void 273 e500_cnputc(dev_t dv, int c) 274 { 275 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 276 int timo = 150000; 277 278 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 279 ; 280 281 com0addr[com_data] = c; 282 __asm("mbar"); 283 284 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 285 ; 286 } 287 288 static void * 289 gur_tlb_mapiodev(paddr_t pa, psize_t len) 290 { 291 if (pa < gur_bst.pbs_offset) 292 return NULL; 293 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 294 return NULL; 295 return (void *)pa; 296 } 297 298 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t) = gur_tlb_mapiodev; 299 300 static void 301 e500_cpu_reset(void) 302 { 303 __asm volatile("sync"); 304 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 305 __asm volatile("msync;isync"); 306 } 307 308 static psize_t 309 memprobe(vaddr_t endkernel) 310 { 311 phys_ram_seg_t *mr; 312 313 /* 314 * First we need to find out how much physical memory we have. 315 * We could let our bootloader tell us, but it's almost as easy 316 * to ask the DDR memory controller. 317 */ 318 mr = physmemr; 319 #if 1 320 for (u_int i = 0; i < 4; i++) { 321 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 322 if (v & CS_CONFIG_EN) { 323 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 324 mr->start = BNDS_SA_GET(v); 325 mr->size = BNDS_SIZE_GET(v); 326 mr++; 327 } 328 } 329 330 if (mr == physmemr) 331 panic("no memory configured!"); 332 #else 333 mr->start = 0; 334 mr->size = 32 << 20; 335 mr++; 336 #endif 337 338 /* 339 * Sort memory regions from low to high and coalesce adjacent regions 340 */ 341 u_int cnt = mr - physmemr; 342 if (cnt > 1) { 343 for (u_int i = 0; i < cnt - 1; i++) { 344 for (u_int j = i + 1; j < cnt; j++) { 345 if (physmemr[j].start < physmemr[i].start) { 346 phys_ram_seg_t tmp = physmemr[i]; 347 physmemr[i] = physmemr[j]; 348 physmemr[j] = tmp; 349 } 350 } 351 } 352 mr = physmemr; 353 for (u_int i = 0; i < cnt; i++, mr++) { 354 if (mr->start + mr->size == mr[1].start) { 355 mr->size += mr[1].size; 356 for (u_int j = 1; j < cnt - i; j++) 357 mr[j] = mr[j+1]; 358 cnt--; 359 } 360 } 361 } 362 363 /* 364 * Copy physical memory to available memory. 365 */ 366 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 367 368 /* 369 * Adjust available memory to skip kernel at start of memory. 370 */ 371 availmemr[0].size -= endkernel - availmemr[0].start; 372 availmemr[0].start = endkernel; 373 374 /* 375 * Steal pages at the end of memory for the kernel message buffer. 376 */ 377 availmemr[cnt-1].size -= round_page(MSGBUFSIZE); 378 msgbuf_paddr = 379 (uintptr_t)(availmemr[cnt-1].start + availmemr[cnt-1].size); 380 381 /* 382 * Calculate physmem. 383 */ 384 for (u_int i = 0; i < cnt; i++) 385 physmem += atop(physmemr[i].size); 386 387 nmemr = cnt; 388 return physmemr[cnt-1].start + physmemr[cnt-1].size; 389 } 390 391 void 392 consinit(void) 393 { 394 static bool attached = false; 395 396 if (attached) 397 return; 398 attached = true; 399 400 if (comcnfreq == -1) { 401 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 402 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 403 comcnfreq = e500_sys_clk * plat_ratio; 404 printf(" comcnfreq=%u", comcnfreq); 405 } 406 407 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 408 COM_TYPE_NORMAL, comcnmode); 409 } 410 411 void 412 cpu_probe_cache(void) 413 { 414 struct cpu_info * const ci = curcpu(); 415 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 416 417 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 418 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 419 420 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 421 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 422 423 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 424 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 425 } else { 426 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 427 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 428 } 429 430 #ifdef DEBUG 431 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 432 if ((L1CSR_CE & l1csr0) == 0) 433 printf(" DC=off"); 434 435 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 436 if ((L1CSR_CE & l1csr1) == 0) 437 printf(" IC=off"); 438 #endif 439 } 440 441 static const char * 442 socname(uint32_t svr) 443 { 444 svr &= ~0x80000; 445 switch (svr >> 8) { 446 case SVR_MPC8548v2 >> 8: return "MPC8548"; 447 case SVR_MPC8547v2 >> 8: return "MPC8547"; 448 case SVR_MPC8545v2 >> 8: return "MPC8545"; 449 case SVR_MPC8543v2 >> 8: return "MPC8543"; 450 case SVR_MPC8544v1 >> 8: return "MPC8544"; 451 case SVR_MPC8536v1 >> 8: return "MPC8536"; 452 case SVR_MPC8572 >> 8: return "MPC8572"; 453 default: 454 panic("%s: unknown SVR %#x", __func__, svr); 455 } 456 } 457 458 static void 459 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 460 { 461 static const char units[16] = "KKKKKMMMMMGGGGGT"; 462 463 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 464 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 465 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 466 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 467 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 468 469 aprint_normal_dev(self, "%s:", name); 470 471 aprint_normal(" %u", nentries); 472 if (TLBCFG_AVAIL_P(tlbcfg)) { 473 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 474 minsize, maxsize, units[maxsize_log4k]); 475 } else { 476 aprint_normal(" fixed-size (%uKB)", minsize); 477 } 478 if (assoc == 0 || assoc == nentries) 479 aprint_normal(" fully"); 480 else 481 aprint_normal(" %u-way set", assoc); 482 aprint_normal(" associative entries\n"); 483 } 484 485 static void 486 e500_cpu_attach(device_t self, u_int instance) 487 { 488 struct cpu_info * const ci = &cpu_info[instance]; 489 490 KASSERT(instance == 0); 491 self->dv_private = ci; 492 493 ci->ci_cpuid = instance; 494 ci->ci_dev = self; 495 //ci->ci_idlespin = cpu_idlespin; 496 if (instance > 0) { 497 ci->ci_idepth = -1; 498 cpu_probe_cache(); 499 } 500 501 uint64_t freq = board_info_get_number("processor-frequency"); 502 char freqbuf[10]; 503 if (freq >= 999500000) { 504 const uint32_t freq32 = (freq + 500000) / 10000000; 505 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 506 freq32 / 100, freq32 % 100); 507 } else { 508 const uint32_t freq32 = (freq + 500000) / 1000000; 509 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 510 } 511 512 const uint32_t pvr = mfpvr(); 513 const uint32_t svr = mfspr(SPR_SVR); 514 const uint32_t pir = mfspr(SPR_PIR); 515 516 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 517 "ID %u%s\n", 518 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 519 (svr >> 4) & 15, svr & 15, 520 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 521 (pvr >> 4) & 15, pvr & 15, 522 pir, (pir == 0 ? " (Primary)" : "")); 523 524 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 525 aprint_normal_dev(self, 526 "%uKB/%uB %u-way L1 %s cache\n", 527 L1CFG_CSIZE_GET(l1cfg0) >> 10, 528 32 << L1CFG_CBSIZE_GET(l1cfg0), 529 L1CFG_CNWAY_GET(l1cfg0), 530 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 531 ? "data" : "unified"); 532 533 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 534 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 535 aprint_normal_dev(self, 536 "%uKB/%uB %u-way L1 %s cache\n", 537 L1CFG_CSIZE_GET(l1cfg1) >> 10, 538 32 << L1CFG_CBSIZE_GET(l1cfg1), 539 L1CFG_CNWAY_GET(l1cfg1), 540 "instruction"); 541 } 542 543 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 544 aprint_normal_dev(self, 545 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 546 MMUCFG_NTLBS_GET(mmucfg) + 1, 547 MMUCFG_NPIDS_GET(mmucfg), 548 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 549 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 550 551 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 552 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 553 554 intr_cpu_init(ci); 555 cpu_evcnt_attach(ci); 556 } 557 558 static void 559 calltozero(void) 560 { 561 panic("call to 0 from %p", __builtin_return_address(0)); 562 } 563 564 void 565 initppc(vaddr_t startkernel, vaddr_t endkernel) 566 { 567 struct cpu_info * const ci = curcpu(); 568 struct cpu_softc * const cpu = ci->ci_softc; 569 570 cn_tab = &e500_earlycons; 571 printf(" initppc<enter>"); 572 573 const register_t hid0 = mfspr(SPR_HID0); 574 mtspr(SPR_HID0, hid0 | HID0_TBEN | HID0_EMCP); 575 #ifdef CADMUS 576 /* 577 * Need to cache this from cadmus since we need to unmap cadmus since 578 * it falls in the middle of kernel address space. 579 */ 580 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 581 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 582 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 583 printf(" cadmus_pci=%#x", cadmus_pci); 584 printf(" cadmus_csr=%#x", cadmus_csr); 585 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 586 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 587 e500_sys_clk *= 2; 588 } 589 #endif 590 #ifdef PIXIS 591 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 592 printf(" pixis_spd=%#x ", pixis_spd); 593 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 594 #endif 595 printf(" porpllsr=0x%08x", 596 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 597 printf(" sys_clk=%"PRIu64, e500_sys_clk); 598 599 /* 600 * Make sure arguments are page aligned. 601 */ 602 startkernel = trunc_page(startkernel); 603 endkernel = round_page(endkernel); 604 605 /* 606 * Initialize the bus space tag used to access the 85xx general 607 * utility registers. It doesn't need to be extent protected. 608 * We know the GUR is mapped via a TLB1 entry so we add a limited 609 * mapiodev which allows mappings in GUR space. 610 */ 611 CTASSERT(offsetof(struct tlb_md_ops, md_tlb_mapiodev) == 0); 612 cpu_md_ops.md_tlb_ops = (const void *)&early_tlb_mapiodev; 613 bus_space_init(&gur_bst, NULL, NULL, 0); 614 cpu->cpu_bst = &gur_bst; 615 cpu->cpu_bsh = gur_bsh; 616 617 /* 618 * Attach the console early, really early. 619 */ 620 consinit(); 621 622 /* 623 * Reset the PIC to a known state. 624 */ 625 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 626 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 627 ; 628 #if 0 629 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 630 #endif 631 printf(" openpic-reset(ctpr=%u)", 632 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 633 634 /* 635 * fill in with an absolute branch to a routine that will panic. 636 */ 637 *(int *)0 = 0x48000002 | (int) calltozero; 638 639 /* 640 * Get the cache sizes. 641 */ 642 cpu_probe_cache(); 643 printf(" cache(DC=%u/%u,IC=%u/%u)", 644 ci->ci_ci.dcache_size >> 10, 645 ci->ci_ci.dcache_line_size, 646 ci->ci_ci.icache_size >> 10, 647 ci->ci_ci.icache_line_size); 648 649 /* 650 * Now find out how much memory is attached 651 */ 652 pmemsize = memprobe(endkernel); 653 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 654 655 /* 656 * Now we need cleanout the TLB of stuff that we don't need. 657 */ 658 e500_tlb_init(endkernel, pmemsize); 659 printf(" e500_tlbinit(%#lx,%zuMB)", 660 endkernel, (size_t) (pmemsize >> 20)); 661 662 /* 663 * 664 */ 665 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 666 printf(" hid1=%#lx", mfspr(SPR_HID1)); 667 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 668 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 669 670 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 671 672 /* 673 * Initialize the message buffer. 674 */ 675 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 676 printf(" msgbuf=%p", (void *)msgbuf_paddr); 677 678 /* 679 * Initialize exception vectors and interrupts 680 */ 681 exception_init(&e500_intrsw); 682 printf(" exception_init=%p", &e500_intrsw); 683 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 684 685 /* 686 * Set the page size. 687 */ 688 uvm_setpagesize(); 689 690 /* 691 * Initialize the pmap. 692 */ 693 pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 694 695 /* 696 * Let's take all the indirect calls via our stubs and patch 697 * them to be direct calls. 698 */ 699 booke_fixup_stubs(); 700 #if 0 701 /* 702 * As a debug measure we can change the TLB entry that maps all of 703 * memory to one that encompasses the 64KB with the kernel vectors. 704 * All other pages will be soft faulted into the TLB as needed. 705 */ 706 const uint32_t saved_mas0 = mfspr(SPR_MAS0); 707 mtspr(SPR_MAS6, 0); 708 __asm volatile("tlbsx\t0, %0" :: "b"(startkernel)); 709 uint32_t mas0 = mfspr(SPR_MAS0); 710 uint32_t mas1 = mfspr(SPR_MAS1); 711 uint32_t mas2 = mfspr(SPR_MAS2); 712 uint32_t mas3 = mfspr(SPR_MAS3); 713 KASSERT(mas3 & MAS3_SW); 714 KASSERT(mas3 & MAS3_SR); 715 KASSERT(mas3 & MAS3_SX); 716 mas1 = (mas1 & ~MAS1_TSIZE) | MASX_TSIZE_64KB; 717 pt_entry_t xpn_mask = ~0 << (10 + 2 * MASX_TSIZE_GET(mas1)); 718 mas2 = (mas2 & ~(MAS2_EPN )) | (startkernel & xpn_mask); 719 mas3 = (mas3 & ~(MAS3_RPN|MAS3_SW)) | (startkernel & xpn_mask); 720 printf(" %#lx=<%#x,%#x,%#x,%#x>", startkernel, mas0, mas1, mas2, mas3); 721 #if 1 722 mtspr(SPR_MAS1, mas1); 723 mtspr(SPR_MAS2, mas2); 724 mtspr(SPR_MAS3, mas3); 725 extern void tlbwe(void); 726 tlbwe(); 727 mtspr(SPR_MAS0, saved_mas0); 728 printf("(ok)"); 729 #endif 730 #endif 731 732 /* 733 * Set some more MD helpers 734 */ 735 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 736 cpu_md_ops.md_device_register = e500_device_register; 737 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 738 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 739 #if NGPIO > 0 740 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 741 #endif 742 743 printf(" initppc done!\n"); 744 } 745 746 #ifdef MPC8548 747 static const char * const mpc8548cds_extirq_names[] = { 748 [0] = "pci inta", 749 [1] = "pci intb", 750 [2] = "pci intc", 751 [3] = "pci intd", 752 [4] = "irq4", 753 [5] = "gige phy", 754 [6] = "atm phy", 755 [7] = "cpld", 756 [8] = "irq8", 757 [9] = "nvram", 758 [10] = "debug", 759 [11] = "pci2 inta", 760 }; 761 #endif 762 763 static const char * const mpc85xx_extirq_names[] = { 764 [0] = "extirq 0", 765 [1] = "extirq 1", 766 [2] = "extirq 2", 767 [3] = "extirq 3", 768 [4] = "extirq 4", 769 [5] = "extirq 5", 770 [6] = "extirq 6", 771 [7] = "extirq 7", 772 [8] = "extirq 8", 773 [9] = "extirq 9", 774 [10] = "extirq 10", 775 [11] = "extirq 11", 776 }; 777 778 static void 779 mpc85xx_extirq_setup(void) 780 { 781 #ifdef MPC8548 782 const char * const * names = mpc8548cds_extirq_names; 783 const size_t n = __arraycount(mpc8548cds_extirq_names); 784 #else 785 const char * const * names = mpc85xx_extirq_names; 786 const size_t n = __arraycount(mpc85xx_extirq_names); 787 #endif 788 prop_array_t extirqs = prop_array_create_with_capacity(n); 789 for (u_int i = 0; i < n; i++) { 790 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 791 prop_array_set(extirqs, i, ps); 792 prop_object_release(ps); 793 } 794 board_info_add_object("external-irqs", extirqs); 795 prop_object_release(extirqs); 796 } 797 798 static void 799 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 800 { 801 prop_dictionary_t pci_intmap = prop_dictionary_create(); 802 KASSERT(pci_intmap != NULL); 803 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 804 KASSERT(mask != NULL); 805 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 806 prop_object_release(mask); 807 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 808 KASSERT(pn_ist != NULL); 809 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 810 KASSERT(pn_intr != NULL); 811 prop_dictionary_t entry = prop_dictionary_create(); 812 KASSERT(entry != NULL); 813 prop_dictionary_set(entry, "interrupt", pn_intr); 814 prop_dictionary_set(entry, "type", pn_ist); 815 prop_dictionary_set(pci_intmap, "000000", entry); 816 prop_object_release(pn_intr); 817 prop_object_release(entry); 818 va_list ap; 819 va_start(ap, inta); 820 u_int intrinc = __LOWEST_SET_BIT(intmask); 821 for (u_int i = 0; i < intmask; i += intrinc) { 822 char prop_name[12]; 823 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 824 entry = prop_dictionary_create(); 825 KASSERT(entry != NULL); 826 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 827 KASSERT(pn_intr != NULL); 828 prop_dictionary_set(entry, "interrupt", pn_intr); 829 prop_dictionary_set(entry, "type", pn_ist); 830 prop_dictionary_set(pci_intmap, prop_name, entry); 831 prop_object_release(pn_intr); 832 prop_object_release(entry); 833 } 834 va_end(ap); 835 prop_object_release(pn_ist); 836 board_info_add_object(name, pci_intmap); 837 prop_object_release(pci_intmap); 838 } 839 840 void 841 cpu_startup(void) 842 { 843 struct cpu_info * const ci = curcpu(); 844 845 booke_cpu_startup(socname(mfspr(SPR_SVR))); 846 847 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 848 uint32_t plat_ratio = PLAT_RATIO_GET(v); 849 uint32_t e500_ratio = E500_RATIO_GET(v); 850 851 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 852 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 853 854 ci->ci_khz = (cpu_freq + 500) / 1000; 855 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 856 857 board_info_add_bool("pq3"); 858 board_info_add_number("mem-size", pmemsize); 859 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 860 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 861 uint32_t l2banks = l2siz >> 16; 862 #ifdef MPC85555 863 if (e500_get_svr() == (MPC8555v1 >> 16)) { 864 l2siz >>= 1; 865 l2banks >>= 1; 866 } 867 #endif 868 board_info_add_number("l2-cache-size", l2siz); 869 board_info_add_number("l2-cache-line-size", 32); 870 board_info_add_number("l2-cache-banks", l2banks); 871 board_info_add_number("l2-cache-ways", 8); 872 873 board_info_add_number("processor-frequency", cpu_freq); 874 board_info_add_number("bus-frequency", ccb_freq); 875 board_info_add_number("pci-frequency", e500_sys_clk); 876 board_info_add_number("timebase-frequency", ccb_freq / 8); 877 878 #ifdef CADMUS 879 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 880 board_info_add_number("tsec1-phy-addr", phy_base + 0); 881 board_info_add_number("tsec2-phy-addr", phy_base + 1); 882 board_info_add_number("tsec3-phy-addr", phy_base + 2); 883 board_info_add_number("tsec4-phy-addr", phy_base + 3); 884 #else 885 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 886 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 887 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 888 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 889 #endif 890 891 uint64_t macstnaddr = 892 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 893 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 894 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 895 896 #if NPCI > 0 && defined(PCI_MEMBASE) 897 pcimem_ex = extent_create("pcimem", 898 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 899 M_DEVBUF, NULL, 0, EX_WAITOK); 900 #endif 901 #if NPCI > 0 && defined(PCI_IOBASE) 902 pciio_ex = extent_create("pciio", 903 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 904 M_DEVBUF, NULL, 0, EX_WAITOK); 905 #endif 906 mpc85xx_extirq_setup(); 907 /* 908 * PCI-Express virtual wire interrupts on combined with 909 * External IRQ0/1/2/3. 910 */ 911 #if defined(MPC8548) 912 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 913 #endif 914 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) 915 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 916 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 4, 5, 6, 7); 917 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 8, 9, 10, 11); 918 #endif 919 #if defined(MPC8544) || defined(MPC8548) 920 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 0, 1, 2, 3); 921 #endif 922 #if defined(MPC8536) 923 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1, 2, 3, 4); 924 #endif 925 #if defined(MPC8548) 926 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 11, 1, 2, 3); 927 #endif 928 } 929