1 /* $NetBSD: machdep.c,v 1.14 2014/03/24 20:06:32 christos Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2014/03/24 20:06:32 christos Exp $"); 78 79 #define __INTR_PRIVATE 80 81 #include "opt_multiprocessor.h" 82 #include "opt_ddb.h" 83 #include "opt_com.h" 84 #include "opt_execfmt.h" 85 #include "opt_memsize.h" 86 #include "rmixl_pcix.h" 87 #include "rmixl_pcie.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/kernel.h> 92 #include <sys/buf.h> 93 #include <sys/cpu.h> 94 #include <sys/reboot.h> 95 #include <sys/mount.h> 96 #include <sys/kcore.h> 97 #include <sys/boot_flag.h> 98 #include <sys/termios.h> 99 #include <sys/ksyms.h> 100 #include <sys/bus.h> 101 #include <sys/device.h> 102 #include <sys/extent.h> 103 #include <sys/malloc.h> 104 105 #include <uvm/uvm_extern.h> 106 107 #include <dev/cons.h> 108 109 #include "ksyms.h" 110 111 #if NKSYMS || defined(DDB) || defined(LKM) 112 #include <mips/db_machdep.h> 113 #include <ddb/db_extern.h> 114 #endif 115 116 #include <mips/cpu.h> 117 #include <mips/psl.h> 118 #include <mips/cache.h> 119 #include <mips/mips_opcode.h> 120 121 #include "com.h" 122 #if NCOM == 0 123 #error no serial console 124 #endif 125 126 #include <dev/ic/comreg.h> 127 #include <dev/ic/comvar.h> 128 129 #include <mips/include/intr.h> 130 131 #include <mips/rmi/rmixlreg.h> 132 #include <mips/rmi/rmixlvar.h> 133 #include <mips/rmi/rmixl_intr.h> 134 #include <mips/rmi/rmixl_firmware.h> 135 #include <mips/rmi/rmixl_comvar.h> 136 #include <mips/rmi/rmixl_pcievar.h> 137 #include <mips/rmi/rmixl_pcixvar.h> 138 139 #ifdef MACHDEP_DEBUG 140 int machdep_debug=MACHDEP_DEBUG; 141 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 142 #else 143 # define DPRINTF(x) 144 #endif 145 146 #ifndef CONSFREQ 147 # define CONSFREQ 66000000 148 #endif 149 #ifndef CONSPEED 150 # define CONSPEED 38400 151 #endif 152 #ifndef CONMODE 153 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 154 #endif 155 #ifndef CONSADDR 156 # define CONSADDR RMIXL_IO_DEV_UART_1 157 #endif 158 159 int comcnfreq = CONSFREQ; 160 int comcnspeed = CONSPEED; 161 tcflag_t comcnmode = CONMODE; 162 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 163 164 struct rmixl_config rmixl_configuration; 165 166 167 /* 168 * array of tested firmware versions 169 * if you find new ones and they work 170 * please add them 171 */ 172 typedef struct rmiclfw_psb_id { 173 uint64_t psb_version; 174 rmixlfw_psb_type_t psb_type; 175 } rmiclfw_psb_id_t; 176 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 177 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 178 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 179 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 180 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 181 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 182 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 183 }; 184 #define RMICLFW_PSB_VERSIONS_LEN \ 185 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 186 187 /* 188 * storage for fixed extent used to allocate physical address regions 189 * because extent(9) start and end values are u_long, they are only 190 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 191 * address is 40 bits wide. So the "physaddr" map stores regions 192 * in units of megabytes. 193 */ 194 static u_long rmixl_physaddr_storage[ 195 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 196 ]; 197 198 /* Maps for VM objects. */ 199 struct vm_map *phys_map = NULL; 200 201 int netboot; /* Are we netbooting? */ 202 203 204 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 205 u_quad_t mem_cluster_maxaddr; 206 u_int mem_cluster_cnt; 207 208 209 void configure(void); 210 void mach_init(int, int32_t *, void *, int64_t); 211 static uint64_t rmixlfw_init(int64_t); 212 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 213 static void __attribute__((__noreturn__)) rmixl_reset(void); 214 static void rmixl_physaddr_init(void); 215 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 216 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 217 218 219 #ifdef MULTIPROCESSOR 220 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2]); 221 void rmixl_get_wakeup_info(struct rmixl_config *); 222 #ifdef MACHDEP_DEBUG 223 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 224 #endif /* MACHDEP_DEBUG */ 225 #endif /* MULTIPROCESSOR */ 226 static void rmixl_fixup_curcpu(void); 227 228 /* 229 * Do all the stuff that locore normally does before calling main(). 230 */ 231 void 232 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 233 { 234 struct rmixl_config *rcp = &rmixl_configuration; 235 void *kernend; 236 uint64_t memsize; 237 extern char edata[], end[]; 238 239 rmixl_pcr_init_core(); 240 241 /* 242 * Clear the BSS segment. 243 */ 244 kernend = (void *)mips_round_page(end); 245 memset(edata, 0, (char *)kernend - edata); 246 247 /* 248 * Set up the exception vectors and CPU-specific function 249 * vectors early on. We need the wbflush() vector set up 250 * before comcnattach() is called (or at least before the 251 * first printf() after that is called). 252 * Also clears the I+D caches. 253 * 254 * specify chip-specific EIRR/EIMR based spl functions 255 */ 256 #ifdef MULTIPROCESSOR 257 mips_vector_init(&rmixl_splsw, true); 258 #else 259 mips_vector_init(&rmixl_splsw, false); 260 #endif 261 262 /* mips_vector_init initialized mips_options */ 263 cpu_setmodel("%s", mips_options.mips_cpu->cpu_name); 264 265 /* get system info from firmware */ 266 memsize = rmixlfw_init(infop); 267 268 /* set the VM page size */ 269 uvm_setpagesize(); 270 271 physmem = btoc(memsize); 272 273 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 274 275 #if NCOM > 0 276 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 277 COM_TYPE_NORMAL, comcnmode); 278 #endif 279 280 printf("\nNetBSD/rmixl\n"); 281 printf("memsize = %#"PRIx64"\n", memsize); 282 #ifdef MEMLIMIT 283 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 284 #endif 285 286 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 287 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 288 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 289 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 290 rcp->rc_cpu_wakeup_info, 291 rcp->rc_cpu_wakeup_end); 292 printf("userapp_cpu_map: %#"PRIx64"\n", 293 rcp->rc_psb_info.userapp_cpu_map); 294 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 295 { 296 register_t sp; 297 asm volatile ("move %0, $sp\n" : "=r"(sp)); 298 printf("sp: %#"PRIx64"\n", sp); 299 } 300 #endif 301 302 rmixl_physaddr_init(); 303 304 /* 305 * Obtain the cpu frequency 306 * Compute the number of ticks for hz. 307 * Compute the delay divisor. 308 * Double the Hz if this CPU runs at twice the 309 * external/cp0-count frequency 310 */ 311 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 312 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 313 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 314 curcpu()->ci_divisor_delay = 315 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 316 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 317 curcpu()->ci_cpu_freq *= 2; 318 319 /* 320 * Look at arguments passed to us and compute boothowto. 321 * - rmixl firmware gives us a 32 bit argv[i], so adapt 322 * by forcing sign extension in cast to (char *) 323 */ 324 boothowto = RB_AUTOBOOT; 325 for (int i = 1; i < argc; i++) { 326 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 327 int howto; 328 /* Ignore superfluous '-', if there is one */ 329 if (*cp == '-') 330 continue; 331 332 howto = 0; 333 BOOT_FLAG(*cp, howto); 334 if (howto != 0) 335 boothowto |= howto; 336 #ifdef DIAGNOSTIC 337 else 338 printf("bootflag '%c' not recognised\n", *cp); 339 #endif 340 } 341 } 342 #ifdef DIAGNOSTIC 343 printf("boothowto %#x\n", boothowto); 344 #endif 345 346 /* 347 * Reserve pages from the VM system. 348 */ 349 350 /* reserve 0..start..kernend pages */ 351 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 352 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 353 354 /* reserve reset exception vector page */ 355 /* should never be in our clusters anyway... */ 356 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 357 0x1FC00000, 0x1FC00000+NBPG); 358 359 #ifdef MULTIPROCEESOR 360 /* reserve the cpu_wakeup_info area */ 361 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 362 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 363 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 364 #endif 365 366 #ifdef MEMLIMIT 367 /* reserve everything >= MEMLIMIT */ 368 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 369 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 370 #endif 371 372 /* get maximum RAM address from the VM clusters */ 373 mem_cluster_maxaddr = 0; 374 for (u_int i=0; i < mem_cluster_cnt; i++) { 375 u_quad_t tmp = round_page( 376 mem_clusters[i].start + mem_clusters[i].size); 377 if (tmp > mem_cluster_maxaddr) 378 mem_cluster_maxaddr = tmp; 379 } 380 DPRINTF(("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr)); 381 382 /* 383 * Load mem_clusters[] into the VM system. 384 */ 385 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 386 mem_clusters, mem_cluster_cnt, NULL, 0); 387 388 /* 389 * Initialize error message buffer (at end of core). 390 */ 391 mips_init_msgbuf(); 392 393 pmap_bootstrap(); 394 395 /* 396 * Allocate uarea page for lwp0 and set it. 397 */ 398 mips_init_lwp0_uarea(); 399 400 #if defined(DDB) 401 if (boothowto & RB_KDB) 402 Debugger(); 403 #endif 404 /* 405 * store (cpu#0) curcpu in COP0 OSSCRATCH0 406 * used in exception vector 407 */ 408 __asm __volatile("dmtc0 %0,$%1" 409 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 410 #ifdef MULTIPROCESSOR 411 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch); 412 #endif 413 rmixl_fixup_curcpu(); 414 } 415 416 /* 417 * set up Processor Control Regs for this core 418 */ 419 void 420 rmixl_pcr_init_core(void) 421 { 422 uint32_t r; 423 424 #ifdef MULTIPROCESSOR 425 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 426 /* enable MMU clock gating */ 427 /* 4 threads active -- why needed if Global? */ 428 /* enable global TLB mode */ 429 #else 430 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); /* disable all threads except #0 */ 431 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); /* enable MMU clock gating */ 432 /* set single MMU Thread Mode */ 433 /* TLB is partitioned (1 partition) */ 434 #endif 435 436 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 437 r &= ~__BIT(14); /* disable Unaligned Access */ 438 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 439 440 #if defined(DDB) && defined(MIPS_DDB_WATCH) 441 /* 442 * clear IEU_DEFEATURE[DBE] 443 * this enables COP0 watchpoint to trigger T_WATCH exception 444 * instead of signaling JTAG. 445 */ 446 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 447 r &= ~__BIT(7); 448 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 449 #endif 450 } 451 452 #ifdef MULTIPROCESSOR 453 static bool 454 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2]) 455 { 456 size_t offset = load_addr - (intptr_t)&cpu_info_store; 457 458 KASSERT(MIPS_KSEG0_P(load_addr)); 459 KASSERT(offset < sizeof(struct cpu_info)); 460 461 /* 462 * Fixup this direct load cpu_info_store to actually get the current 463 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 464 * relative from the start of struct cpu_info. 465 */ 466 467 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 468 new_insns[0] = (020 << 26) 469 #ifdef _LP64 470 | (1 << 21) /* double move */ 471 #endif 472 | (new_insns[0] & 0x001f0000) 473 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 474 475 /* [1] = [ls][dw] rX, offset(rX) */ 476 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 477 478 return true; 479 } 480 #endif /* MULTIPROCESSOR */ 481 482 /* 483 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 484 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 485 * 486 * the mfc0 is 3 cycles shorter than the load. 487 */ 488 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 489 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 490 #ifdef _LP64 491 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 492 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 493 #else 494 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 495 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 496 #endif 497 #define LOAD_CURCPU_MASK 0xffe0ffff 498 499 static void 500 rmixl_fixup_curcpu(void) 501 { 502 extern uint32_t _ftext[]; 503 extern uint32_t _etext[]; 504 505 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 506 const uint32_t insn = *insnp; 507 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 508 /* 509 * Since the register to loaded is located in bits 510 * 16-20 for the mfc0 and the load instruction we can 511 * just change the instruction bits around it. 512 */ 513 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 514 mips_icache_sync_range((vaddr_t)insnp, 4); 515 } 516 } 517 } 518 519 /* 520 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 521 * 522 * we simply build a new table of segs, then copy it back over the given one 523 * this is inefficient but simple and called only a few times 524 * 525 * note: 'last' here means 1st addr past the end of the segment (start+size) 526 */ 527 static u_int 528 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 529 u_quad_t resv_first, u_quad_t resv_last) 530 { 531 u_quad_t first, last; 532 int new_nsegs=0; 533 int resv_flag; 534 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 535 536 for (u_int i=0; i < nsegs; i++) { 537 resv_flag = 0; 538 first = trunc_page(segs[i].start); 539 last = round_page(segs[i].start + segs[i].size); 540 541 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 542 if ((resv_first <= first) && (resv_last >= last)) { 543 /* whole segment is resverved */ 544 continue; 545 } 546 if ((resv_first > first) && (resv_first < last)) { 547 u_quad_t new_last; 548 549 /* 550 * reserved start in segment 551 * salvage the leading fragment 552 */ 553 resv_flag = 1; 554 new_last = last - (last - resv_first); 555 KASSERT (new_last > first); 556 new_segs[new_nsegs].start = first; 557 new_segs[new_nsegs].size = new_last - first; 558 new_nsegs++; 559 } 560 if ((resv_last > first) && (resv_last < last)) { 561 u_quad_t new_first; 562 563 /* 564 * reserved end in segment 565 * salvage the trailing fragment 566 */ 567 resv_flag = 1; 568 new_first = first + (resv_last - first); 569 KASSERT (last > (new_first + NBPG)); 570 new_segs[new_nsegs].start = new_first; 571 new_segs[new_nsegs].size = last - new_first; 572 new_nsegs++; 573 } 574 if (resv_flag == 0) { 575 /* 576 * nothing reserved here, take it all 577 */ 578 new_segs[new_nsegs].start = first; 579 new_segs[new_nsegs].size = last - first; 580 new_nsegs++; 581 } 582 583 } 584 585 memcpy(segs, new_segs, sizeof(new_segs)); 586 587 return new_nsegs; 588 } 589 590 /* 591 * create an extent for physical address space 592 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 593 * allocate the regions where we have known functions (DRAM, IO, etc) 594 * what remains can be allocated as needed for other stuff 595 * e.g. to configure BARs that are not already initialized and enabled. 596 */ 597 static void 598 rmixl_physaddr_init(void) 599 { 600 struct extent *ext; 601 unsigned long start = 0UL; 602 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 603 u_long base; 604 u_long size; 605 uint32_t r; 606 607 ext = extent_create("physaddr", start, end, 608 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 609 EX_NOWAIT | EX_NOCOALESCE); 610 611 if (ext == NULL) 612 panic("%s: extent_create failed", __func__); 613 614 /* 615 * grab regions per DRAM BARs 616 */ 617 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 618 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 619 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 620 continue; /* not enabled */ 621 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 622 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 623 624 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 625 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 626 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 627 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 628 "failed", __func__, ext, base, size, EX_NOWAIT); 629 } 630 631 /* 632 * get chip-dependent physaddr regions 633 */ 634 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 635 case CIDFL_RMI_TYPE_XLR: 636 #if NRMIXL_PCIX 637 rmixl_physaddr_init_pcix(ext); 638 #endif 639 break; 640 case CIDFL_RMI_TYPE_XLS: 641 #if NRMIXL_PCIE 642 rmixl_physaddr_init_pcie(ext); 643 #endif 644 break; 645 case CIDFL_RMI_TYPE_XLP: 646 /* XXX TBD */ 647 panic("%s: RMI XLP not yet supported", __func__); 648 } 649 650 /* 651 * at this point all regions left in "physaddr" extent 652 * are unused holes in the physical adress space 653 * available for use as needed. 654 */ 655 rmixl_configuration.rc_phys_ex = ext; 656 #ifdef MACHDEP_DEBUG 657 extent_print(ext); 658 #endif 659 } 660 661 static uint64_t 662 rmixlfw_init(int64_t infop) 663 { 664 struct rmixl_config *rcp = &rmixl_configuration; 665 666 #ifdef MULTIPROCESSOR 667 rmixl_get_wakeup_info(rcp); 668 #endif 669 670 infop |= MIPS_KSEG0_START; 671 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 672 673 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 674 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 675 if (rmiclfw_psb_id[i].psb_version == 676 rcp->rc_psb_info.psb_version) { 677 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 678 goto found; 679 } 680 } 681 682 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 683 rmixl_putchar_init(rcp->rc_io_pbase); 684 685 #ifdef DIAGNOSTIC 686 rmixl_puts("\r\nWARNING: untested psb_version: "); 687 rmixl_puthex64(rcp->rc_psb_info.psb_version); 688 rmixl_puts("\r\n"); 689 #endif 690 691 #ifdef MEMSIZE 692 /* XXX trust and use MEMSIZE */ 693 mem_clusters[0].start = 0; 694 mem_clusters[0].size = MEMSIZE; 695 mem_cluster_cnt = 1; 696 return MEMSIZE; 697 #else 698 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 699 cpu_reboot(RB_HALT, NULL); 700 /* NOTREACHED */ 701 #endif 702 703 found: 704 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 705 rmixl_putchar_init(rcp->rc_io_pbase); 706 #ifdef MACHDEP_DEBUG 707 rmixl_puts("\r\ninfop: "); 708 rmixl_puthex64((uint64_t)(intptr_t)infop); 709 #endif 710 #ifdef DIAGNOSTIC 711 rmixl_puts("\r\nrecognized psb_version="); 712 rmixl_puthex64(rcp->rc_psb_info.psb_version); 713 rmixl_puts(", psb_type="); 714 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 715 rmixl_puts("\r\n"); 716 #endif 717 718 return mem_clusters_init( 719 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 720 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 721 } 722 723 void 724 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 725 { 726 #ifdef MACHDEP_DEBUG 727 for (uint32_t i=0; i < map->nmmaps; i++) { 728 rmixl_puthex32(i); 729 rmixl_puts(", "); 730 rmixl_puthex64(map->entry[i].start); 731 rmixl_puts(", "); 732 rmixl_puthex64(map->entry[i].size); 733 rmixl_puts(", "); 734 rmixl_puthex32(map->entry[i].type); 735 rmixl_puts("\r\n"); 736 } 737 #endif 738 } 739 740 /* 741 * mem_clusters_init 742 * 743 * initialize mem_clusters[] table based on memory address mapping 744 * provided by boot firmware. 745 * 746 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 747 * these will be limited by MEMSIZE if it is configured. 748 * if neither are available, just use MEMSIZE. 749 */ 750 static uint64_t 751 mem_clusters_init( 752 rmixlfw_mmap_t *psb_physaddr_map, 753 rmixlfw_mmap_t *avail_mem_map) 754 { 755 rmixlfw_mmap_t *map = NULL; 756 const char *mapname; 757 uint64_t sz; 758 uint64_t sum; 759 u_int cnt; 760 #ifdef MEMSIZE 761 uint64_t memsize = MEMSIZE; 762 #endif 763 764 #ifdef MACHDEP_DEBUG 765 rmixl_puts("psb_physaddr_map: "); 766 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 767 rmixl_puts("\r\n"); 768 #endif 769 if (psb_physaddr_map != NULL) { 770 map = psb_physaddr_map; 771 mapname = "psb_physaddr_map"; 772 rmixlfw_mmap_print(map); 773 } 774 #ifdef DIAGNOSTIC 775 else { 776 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 777 } 778 #endif 779 780 #ifdef MACHDEP_DEBUG 781 rmixl_puts("avail_mem_map: "); 782 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 783 rmixl_puts("\r\n"); 784 #endif 785 if (avail_mem_map != NULL) { 786 map = avail_mem_map; 787 mapname = "avail_mem_map"; 788 rmixlfw_mmap_print(map); 789 } 790 #ifdef DIAGNOSTIC 791 else { 792 rmixl_puts("WARNING: no avail_mem_map\r\n"); 793 } 794 #endif 795 796 if (map == NULL) { 797 #ifndef MEMSIZE 798 rmixl_puts("panic: no firmware memory map, " 799 "must configure MEMSIZE\r\n"); 800 for(;;); /* XXX */ 801 #else 802 #ifdef DIAGNOSTIC 803 rmixl_puts("WARNING: no avail_mem_map, " 804 "using MEMSIZE\r\n"); 805 #endif 806 807 mem_clusters[0].start = 0; 808 mem_clusters[0].size = MEMSIZE; 809 mem_cluster_cnt = 1; 810 return MEMSIZE; 811 #endif /* MEMSIZE */ 812 } 813 814 #ifdef DIAGNOSTIC 815 rmixl_puts("using "); 816 rmixl_puts(mapname); 817 rmixl_puts("\r\n"); 818 #endif 819 #ifdef MACHDEP_DEBUG 820 rmixl_puts("memory clusters:\r\n"); 821 #endif 822 sum = 0; 823 cnt = 0; 824 for (uint32_t i=0; i < map->nmmaps; i++) { 825 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 826 continue; 827 mem_clusters[cnt].start = map->entry[i].start; 828 sz = map->entry[i].size; 829 sum += sz; 830 mem_clusters[cnt].size = sz; 831 #ifdef MACHDEP_DEBUG 832 rmixl_puthex32(i); 833 rmixl_puts(": "); 834 rmixl_puthex64(mem_clusters[cnt].start); 835 rmixl_puts(", "); 836 rmixl_puthex64(sz); 837 rmixl_puts(": "); 838 rmixl_puthex64(sum); 839 rmixl_puts("\r\n"); 840 #endif 841 #ifdef MEMSIZE 842 /* 843 * configurably limit memsize 844 */ 845 if (sum == memsize) 846 break; 847 if (sum > memsize) { 848 uint64_t tmp; 849 850 tmp = sum - memsize; 851 sz -= tmp; 852 sum -= tmp; 853 mem_clusters[cnt].size = sz; 854 cnt++; 855 break; 856 } 857 #endif 858 cnt++; 859 } 860 mem_cluster_cnt = cnt; 861 return sum; 862 } 863 864 #ifdef MULTIPROCESSOR 865 /* 866 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 867 * they do not explicitly give us the size of the wakeup area. 868 * we "know" that firmware loader sets wip->gp thusly: 869 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 870 * so 871 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 872 * Only the "master" cpu runs this function, so 873 * vcpu = wip->master_cpu 874 */ 875 void 876 rmixl_get_wakeup_info(struct rmixl_config *rcp) 877 { 878 volatile rmixlfw_cpu_wakeup_info_t *wip; 879 int32_t scratch_7; 880 intptr_t end; 881 882 __asm__ volatile( 883 ".set push" "\n" 884 ".set noreorder" "\n" 885 ".set mips64" "\n" 886 "dmfc0 %0, $22, 7" "\n" 887 ".set pop" "\n" 888 : "=r"(scratch_7)); 889 890 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 891 (intptr_t)scratch_7; 892 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2));; 893 894 if (wip->valid == 1) { 895 rcp->rc_cpu_wakeup_end = (const void *)end; 896 rcp->rc_cpu_wakeup_info = wip; 897 } 898 }; 899 900 #ifdef MACHDEP_DEBUG 901 static void 902 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 903 { 904 int i; 905 906 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 907 908 printf("cpu_status %#x\n", wip->cpu_status); 909 printf("valid: %d\n", wip->valid); 910 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 911 wip->entry.addr, 912 wip->entry.args, 913 wip->entry.sp, 914 wip->entry.gp); 915 printf("master_cpu %d\n", wip->master_cpu); 916 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 917 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 918 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 919 printf("argc %d\n", wip->argc); 920 printf("argv:"); 921 for (i=0; i < wip->argc; i++) 922 printf(" %#x", wip->argv[i]); 923 printf("\n"); 924 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 925 printf("tlb_map:\n"); 926 for (i=0; i < wip->valid_tlb_entries; i++) { 927 volatile const struct lib_cpu_tlb_mapping *m = 928 &wip->tlb_map[i]; 929 printf(" %d", m->page_size); 930 printf(", %d", m->asid); 931 printf(", %d", m->coherency); 932 printf(", %d", m->coherency); 933 printf(", %d", m->attr); 934 printf(", %#x", m->virt); 935 printf(", %#"PRIx64"\n", m->phys); 936 } 937 printf("elf segs:\n"); 938 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 939 volatile const struct core_segment_info *e = 940 &wip->seg_info[i]; 941 printf(" %#"PRIx64"", e->vaddr); 942 printf(", %#"PRIx64"", e->memsz); 943 printf(", %#x\n", e->flags); 944 } 945 printf("envc %d\n", wip->envc); 946 for (i=0; i < wip->envc; i++) 947 printf(" %#x \"%s\"", wip->envs[i], 948 (char *)(intptr_t)(int32_t)(wip->envs[i])); 949 printf("\n"); 950 printf("app_mode %d\n", wip->app_mode); 951 printf("printk_lock %#x\n", wip->printk_lock); 952 printf("kseg_master %d\n", wip->kseg_master); 953 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 954 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 955 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 956 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 957 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 958 printf("loader_lock %#x\n", wip->loader_lock); 959 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 960 printf("unused_0 %#x\n", wip->unused_0); 961 } 962 #endif /* MACHDEP_DEBUG */ 963 #endif /* MULTIPROCESSOR */ 964 965 void 966 consinit(void) 967 { 968 969 /* 970 * Everything related to console initialization is done 971 * in mach_init(). 972 */ 973 } 974 975 /* 976 * Allocate memory for variable-sized tables, 977 */ 978 void 979 cpu_startup(void) 980 { 981 vaddr_t minaddr, maxaddr; 982 char pbuf[9]; 983 984 /* 985 * Good {morning,afternoon,evening,night}. 986 */ 987 printf("%s%s", copyright, version); 988 format_bytes(pbuf, sizeof(pbuf), ctob((uint64_t)physmem)); 989 printf("total memory = %s\n", pbuf); 990 991 /* 992 * Virtual memory is bootstrapped -- notify the bus spaces 993 * that memory allocation is now safe. 994 */ 995 rmixl_configuration.rc_mallocsafe = 1; 996 997 minaddr = 0; 998 /* 999 * Allocate a submap for physio. 1000 */ 1001 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 1002 VM_PHYS_SIZE, 0, FALSE, NULL); 1003 1004 /* 1005 * (No need to allocate an mbuf cluster submap. Mbuf clusters 1006 * are allocated via the pool allocator, and we use XKSEG to 1007 * map those pages.) 1008 */ 1009 1010 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 1011 printf("avail memory = %s\n", pbuf); 1012 } 1013 1014 int waittime = -1; 1015 1016 void 1017 cpu_reboot(int howto, char *bootstr) 1018 { 1019 1020 /* Take a snapshot before clobbering any registers. */ 1021 savectx(curpcb); 1022 1023 if (cold) { 1024 howto |= RB_HALT; 1025 goto haltsys; 1026 } 1027 1028 /* If "always halt" was specified as a boot flag, obey. */ 1029 if (boothowto & RB_HALT) 1030 howto |= RB_HALT; 1031 1032 boothowto = howto; 1033 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1034 waittime = 0; 1035 vfs_shutdown(); 1036 1037 /* 1038 * If we've been adjusting the clock, the todr 1039 * will be out of synch; adjust it now. 1040 */ 1041 resettodr(); 1042 } 1043 1044 splhigh(); 1045 1046 if (howto & RB_DUMP) 1047 dumpsys(); 1048 1049 haltsys: 1050 doshutdownhooks(); 1051 1052 if (howto & RB_HALT) { 1053 printf("\n"); 1054 printf("The operating system has halted.\n"); 1055 printf("Please press any key to reboot.\n\n"); 1056 cnpollc(1); /* For proper keyboard command handling */ 1057 cngetc(); 1058 cnpollc(0); 1059 } 1060 1061 printf("rebooting...\n\n"); 1062 1063 rmixl_reset(); 1064 } 1065 1066 /* 1067 * goodbye world 1068 */ 1069 void __attribute__((__noreturn__)) 1070 rmixl_reset(void) 1071 { 1072 uint32_t r; 1073 1074 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1075 r |= RMIXL_GPIO_RESET_RESET; 1076 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1077 1078 printf("soft reset failed, spinning...\n"); 1079 for (;;); 1080 } 1081