1 /* $NetBSD: machdep.c,v 1.20 2021/08/02 12:56:22 andvar Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1988 University of Utah. 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This code is derived from software contributed to Berkeley by 44 * the Systems Programming Group of the University of Utah Computer 45 * Science Department, The Mach Operating System project at 46 * Carnegie-Mellon University and Ralph Campbell. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 73 * from: Utah Hdr: machdep.c 1.63 91/04/24 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.20 2021/08/02 12:56:22 andvar Exp $"); 78 79 #define __INTR_PRIVATE 80 81 #include "opt_multiprocessor.h" 82 #include "opt_ddb.h" 83 #include "opt_com.h" 84 #include "opt_execfmt.h" 85 #include "opt_memsize.h" 86 #include "rmixl_pcix.h" 87 #include "rmixl_pcie.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/kernel.h> 92 #include <sys/buf.h> 93 #include <sys/cpu.h> 94 #include <sys/reboot.h> 95 #include <sys/mount.h> 96 #include <sys/kcore.h> 97 #include <sys/boot_flag.h> 98 #include <sys/termios.h> 99 #include <sys/ksyms.h> 100 #include <sys/bus.h> 101 #include <sys/device.h> 102 #include <sys/extent.h> 103 #include <sys/malloc.h> 104 105 #include <uvm/uvm_extern.h> 106 107 #include <dev/cons.h> 108 109 #include "ksyms.h" 110 111 #if NKSYMS || defined(DDB) || defined(LKM) 112 #include <mips/db_machdep.h> 113 #include <ddb/db_extern.h> 114 #endif 115 116 #include <mips/cpu.h> 117 #include <mips/psl.h> 118 #include <mips/cache.h> 119 #include <mips/mips_opcode.h> 120 121 #include "com.h" 122 #if NCOM == 0 123 #error no serial console 124 #endif 125 126 #include <dev/ic/comreg.h> 127 #include <dev/ic/comvar.h> 128 129 #include <mips/include/intr.h> 130 131 #include <mips/rmi/rmixlreg.h> 132 #include <mips/rmi/rmixlvar.h> 133 #include <mips/rmi/rmixl_intr.h> 134 #include <mips/rmi/rmixl_firmware.h> 135 #include <mips/rmi/rmixl_comvar.h> 136 #include <mips/rmi/rmixl_pcievar.h> 137 #include <mips/rmi/rmixl_pcixvar.h> 138 139 #ifdef MACHDEP_DEBUG 140 int machdep_debug=MACHDEP_DEBUG; 141 # define DPRINTF(x) do { if (machdep_debug) printf x ; } while(0) 142 #else 143 # define DPRINTF(x) 144 #endif 145 146 #ifndef CONSFREQ 147 # define CONSFREQ 66000000 148 #endif 149 #ifndef CONSPEED 150 # define CONSPEED 38400 151 #endif 152 #ifndef CONMODE 153 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 154 #endif 155 #ifndef CONSADDR 156 # define CONSADDR RMIXL_IO_DEV_UART_1 157 #endif 158 159 int comcnfreq = CONSFREQ; 160 int comcnspeed = CONSPEED; 161 tcflag_t comcnmode = CONMODE; 162 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 163 164 struct rmixl_config rmixl_configuration; 165 166 167 /* 168 * array of tested firmware versions 169 * if you find new ones and they work 170 * please add them 171 */ 172 typedef struct rmiclfw_psb_id { 173 uint64_t psb_version; 174 rmixlfw_psb_type_t psb_type; 175 } rmiclfw_psb_id_t; 176 static rmiclfw_psb_id_t rmiclfw_psb_id[] = { 177 { 0x4958d4fb00000056ULL, PSB_TYPE_RMI }, 178 { 0x4aacdb6a00000056ULL, PSB_TYPE_RMI }, 179 { 0x4b67d03200000056ULL, PSB_TYPE_RMI }, 180 { 0x4c17058b00000056ULL, PSB_TYPE_RMI }, 181 { 0x49a5a8fa00000056ULL, PSB_TYPE_DELL }, 182 { 0x4b8ead3100000056ULL, PSB_TYPE_DELL }, 183 }; 184 #define RMICLFW_PSB_VERSIONS_LEN \ 185 (sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0])) 186 187 /* 188 * storage for fixed extent used to allocate physical address regions 189 * because extent(9) start and end values are u_long, they are only 190 * 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical 191 * address is 40 bits wide. So the "physaddr" map stores regions 192 * in units of megabytes. 193 */ 194 static u_long rmixl_physaddr_storage[ 195 EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long) 196 ]; 197 198 /* Maps for VM objects. */ 199 struct vm_map *phys_map = NULL; 200 201 int netboot; /* Are we netbooting? */ 202 203 204 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 205 u_quad_t mem_cluster_maxaddr; 206 u_int mem_cluster_cnt; 207 208 209 void configure(void); 210 void mach_init(int, int32_t *, void *, int64_t); 211 static uint64_t rmixlfw_init(int64_t); 212 static uint64_t mem_clusters_init(rmixlfw_mmap_t *, rmixlfw_mmap_t *); 213 static void __attribute__((__noreturn__)) rmixl_reset(void); 214 static void rmixl_physaddr_init(void); 215 static u_int ram_seg_resv(phys_ram_seg_t *, u_int, u_quad_t, u_quad_t); 216 void rmixlfw_mmap_print(rmixlfw_mmap_t *); 217 218 219 #ifdef MULTIPROCESSOR 220 static bool rmixl_fixup_cop0_oscratch(int32_t, uint32_t [2], void *); 221 void rmixl_get_wakeup_info(struct rmixl_config *); 222 #ifdef MACHDEP_DEBUG 223 static void rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *); 224 #endif /* MACHDEP_DEBUG */ 225 #endif /* MULTIPROCESSOR */ 226 static void rmixl_fixup_curcpu(void); 227 228 /* 229 * Do all the stuff that locore normally does before calling main(). 230 */ 231 void 232 mach_init(int argc, int32_t *argv, void *envp, int64_t infop) 233 { 234 struct rmixl_config *rcp = &rmixl_configuration; 235 void *kernend; 236 uint64_t memsize; 237 extern char edata[], end[]; 238 239 rmixl_pcr_init_core(); 240 241 /* 242 * Clear the BSS segment. 243 */ 244 kernend = (void *)mips_round_page(end); 245 memset(edata, 0, (char *)kernend - edata); 246 247 /* 248 * Set up the exception vectors and CPU-specific function 249 * vectors early on. We need the wbflush() vector set up 250 * before comcnattach() is called (or at least before the 251 * first printf() after that is called). 252 * Also clears the I+D caches. 253 * 254 * specify chip-specific EIRR/EIMR based spl functions 255 */ 256 #ifdef MULTIPROCESSOR 257 mips_vector_init(&rmixl_splsw, true); 258 #else 259 mips_vector_init(&rmixl_splsw, false); 260 #endif 261 262 /* mips_vector_init initialized mips_options */ 263 cpu_setmodel("%s", mips_options.mips_cpu->cpu_name); 264 265 /* get system info from firmware */ 266 memsize = rmixlfw_init(infop); 267 268 uvm_md_init(); 269 270 physmem = btoc(memsize); 271 272 rmixl_obio_eb_bus_mem_init(&rcp->rc_obio_eb_memt, rcp); 273 274 #if NCOM > 0 275 rmixl_com_cnattach(comcnaddr, comcnspeed, comcnfreq, 276 COM_TYPE_NORMAL, comcnmode); 277 #endif 278 279 printf("\nNetBSD/rmixl\n"); 280 printf("memsize = %#"PRIx64"\n", memsize); 281 #ifdef MEMLIMIT 282 printf("memlimit = %#"PRIx64"\n", (uint64_t)MEMLIMIT); 283 #endif 284 285 #if defined(MULTIPROCESSOR) && defined(MACHDEP_DEBUG) 286 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info); 287 rmixl_wakeup_info_print(rcp->rc_cpu_wakeup_info + 1); 288 printf("cpu_wakeup_info %p, cpu_wakeup_end %p\n", 289 rcp->rc_cpu_wakeup_info, 290 rcp->rc_cpu_wakeup_end); 291 printf("userapp_cpu_map: %#"PRIx64"\n", 292 rcp->rc_psb_info.userapp_cpu_map); 293 printf("wakeup: %#"PRIx64"\n", rcp->rc_psb_info.wakeup); 294 { 295 register_t sp; 296 asm volatile ("move %0, $sp\n" : "=r"(sp)); 297 printf("sp: %#"PRIx64"\n", sp); 298 } 299 #endif 300 301 rmixl_physaddr_init(); 302 303 /* 304 * Obtain the cpu frequency 305 * Compute the number of ticks for hz. 306 * Compute the delay divisor. 307 * Double the Hz if this CPU runs at twice the 308 * external/cp0-count frequency 309 */ 310 curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency; 311 curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq; 312 curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz; 313 curcpu()->ci_divisor_delay = 314 ((curcpu()->ci_cpu_freq + 500000) / 1000000); 315 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 316 curcpu()->ci_cpu_freq *= 2; 317 318 /* 319 * Look at arguments passed to us and compute boothowto. 320 * - rmixl firmware gives us a 32 bit argv[i], so adapt 321 * by forcing sign extension in cast to (char *) 322 */ 323 boothowto = RB_AUTOBOOT; 324 for (int i = 1; i < argc; i++) { 325 for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) { 326 int howto; 327 /* Ignore superfluous '-', if there is one */ 328 if (*cp == '-') 329 continue; 330 331 howto = 0; 332 BOOT_FLAG(*cp, howto); 333 if (howto != 0) 334 boothowto |= howto; 335 #ifdef DIAGNOSTIC 336 else 337 printf("bootflag '%c' not recognised\n", *cp); 338 #endif 339 } 340 } 341 #ifdef DIAGNOSTIC 342 printf("boothowto %#x\n", boothowto); 343 #endif 344 345 /* 346 * Reserve pages from the VM system. 347 */ 348 349 /* reserve 0..start..kernend pages */ 350 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 351 0, round_page(MIPS_KSEG0_TO_PHYS(kernend))); 352 353 /* reserve reset exception vector page */ 354 /* should never be in our clusters anyway... */ 355 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 356 0x1FC00000, 0x1FC00000+NBPG); 357 358 #ifdef MULTIPROCEESOR 359 /* reserve the cpu_wakeup_info area */ 360 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 361 (u_quad_t)trunc_page(rcp->rc_cpu_wakeup_info), 362 (u_quad_t)round_page(rcp->rc_cpu_wakeup_end)); 363 #endif 364 365 #ifdef MEMLIMIT 366 /* reserve everything >= MEMLIMIT */ 367 mem_cluster_cnt = ram_seg_resv(mem_clusters, mem_cluster_cnt, 368 (u_quad_t)MEMLIMIT, (u_quad_t)~0); 369 #endif 370 371 /* get maximum RAM address from the VM clusters */ 372 mem_cluster_maxaddr = 0; 373 for (u_int i=0; i < mem_cluster_cnt; i++) { 374 u_quad_t tmp = round_page( 375 mem_clusters[i].start + mem_clusters[i].size); 376 if (tmp > mem_cluster_maxaddr) 377 mem_cluster_maxaddr = tmp; 378 } 379 DPRINTF(("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr)); 380 381 /* 382 * Load mem_clusters[] into the VM system. 383 */ 384 mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend, 385 mem_clusters, mem_cluster_cnt, NULL, 0); 386 387 /* 388 * Initialize error message buffer (at end of core). 389 */ 390 mips_init_msgbuf(); 391 392 pmap_bootstrap(); 393 394 /* 395 * Allocate uarea page for lwp0 and set it. 396 */ 397 mips_init_lwp0_uarea(); 398 399 #if defined(DDB) 400 if (boothowto & RB_KDB) 401 Debugger(); 402 #endif 403 /* 404 * store (cpu#0) curcpu in COP0 OSSCRATCH0 405 * used in exception vector 406 */ 407 __asm __volatile("dmtc0 %0,$%1" 408 :: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH)); 409 #ifdef MULTIPROCESSOR 410 mips_fixup_exceptions(rmixl_fixup_cop0_oscratch, NULL); 411 #endif 412 rmixl_fixup_curcpu(); 413 } 414 415 /* 416 * set up Processor Control Regs for this core 417 */ 418 void 419 rmixl_pcr_init_core(void) 420 { 421 uint32_t r; 422 423 #ifdef MULTIPROCESSOR 424 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0)); 425 /* enable MMU clock gating */ 426 /* 4 threads active -- why needed if Global? */ 427 /* enable global TLB mode */ 428 #else 429 rmixl_mtcr(RMIXL_PCR_THREADEN, 1); /* disable all threads except #0 */ 430 rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); /* enable MMU clock gating */ 431 /* set single MMU Thread Mode */ 432 /* TLB is partitioned (1 partition) */ 433 #endif 434 435 r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0); 436 r &= ~__BIT(14); /* disable Unaligned Access */ 437 rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r); 438 439 #if defined(DDB) && defined(MIPS_DDB_WATCH) 440 /* 441 * clear IEU_DEFEATURE[DBE] 442 * this enables COP0 watchpoint to trigger T_WATCH exception 443 * instead of signaling JTAG. 444 */ 445 r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE); 446 r &= ~__BIT(7); 447 rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r); 448 #endif 449 } 450 451 #ifdef MULTIPROCESSOR 452 static bool 453 rmixl_fixup_cop0_oscratch(int32_t load_addr, uint32_t new_insns[2], void *arg) 454 { 455 size_t offset = load_addr - (intptr_t)&cpu_info_store; 456 457 KASSERT(MIPS_KSEG0_P(load_addr)); 458 KASSERT(offset < sizeof(struct cpu_info)); 459 460 /* 461 * Fixup this direct load cpu_info_store to actually get the current 462 * CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be 463 * relative from the start of struct cpu_info. 464 */ 465 466 /* [0] = [d]mfc0 rX, $22 (OSScratch) */ 467 new_insns[0] = (020 << 26) 468 #ifdef _LP64 469 | (1 << 21) /* double move */ 470 #endif 471 | (new_insns[0] & 0x001f0000) 472 | (MIPS_COP_0_OSSCRATCH << 11) | (0 << 0); 473 474 /* [1] = [ls][dw] rX, offset(rX) */ 475 new_insns[1] = (new_insns[1] & 0xffff0000) | offset; 476 477 return true; 478 } 479 #endif /* MULTIPROCESSOR */ 480 481 /* 482 * The following changes all lX rN, L_CPU(MIPS_CURLWP) [curlwp->l_cpu] 483 * to [d]mfc0 rN, $22 [MIPS_COP_0_OSSCRATCH] 484 * 485 * the mfc0 is 3 cycles shorter than the load. 486 */ 487 #define LOAD_CURCPU_0 ((MIPS_CURLWP_REG << 21) | offsetof(lwp_t, l_cpu)) 488 #define MFC0_CURCPU_0 ((OP_COP0 << 26) | (MIPS_COP_0_OSSCRATCH << 11)) 489 #ifdef _LP64 490 #define LOAD_CURCPU ((uint32_t)(OP_LD << 26) | LOAD_CURCPU_0) 491 #define MFC0_CURCPU ((uint32_t)(OP_DMF << 21) | MFC0_CURCPU_0) 492 #else 493 #define LOAD_CURCPU ((uint32_t)(OP_LW << 26) | LOAD_CURCPU_0) 494 #define MFC0_CURCPU ((uint32_t)(OP_MF << 21) | MFC0_CURCPU_0) 495 #endif 496 #define LOAD_CURCPU_MASK 0xffe0ffff 497 498 static void 499 rmixl_fixup_curcpu(void) 500 { 501 extern uint32_t _ftext[]; 502 extern uint32_t _etext[]; 503 504 for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) { 505 const uint32_t insn = *insnp; 506 if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) { 507 /* 508 * Since the register to loaded is located in bits 509 * 16-20 for the mfc0 and the load instruction we can 510 * just change the instruction bits around it. 511 */ 512 *insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU; 513 mips_icache_sync_range((vaddr_t)insnp, 4); 514 } 515 } 516 } 517 518 /* 519 * ram_seg_resv - cut reserved regions out of segs, fragmenting as needed 520 * 521 * we simply build a new table of segs, then copy it back over the given one 522 * this is inefficient but simple and called only a few times 523 * 524 * note: 'last' here means 1st addr past the end of the segment (start+size) 525 */ 526 static u_int 527 ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs, 528 u_quad_t resv_first, u_quad_t resv_last) 529 { 530 u_quad_t first, last; 531 int new_nsegs=0; 532 int resv_flag; 533 phys_ram_seg_t new_segs[VM_PHYSSEG_MAX]; 534 535 for (u_int i=0; i < nsegs; i++) { 536 resv_flag = 0; 537 first = trunc_page(segs[i].start); 538 last = round_page(segs[i].start + segs[i].size); 539 540 KASSERT(new_nsegs < VM_PHYSSEG_MAX); 541 if ((resv_first <= first) && (resv_last >= last)) { 542 /* whole segment is resverved */ 543 continue; 544 } 545 if ((resv_first > first) && (resv_first < last)) { 546 u_quad_t new_last; 547 548 /* 549 * reserved start in segment 550 * salvage the leading fragment 551 */ 552 resv_flag = 1; 553 new_last = last - (last - resv_first); 554 KASSERT (new_last > first); 555 new_segs[new_nsegs].start = first; 556 new_segs[new_nsegs].size = new_last - first; 557 new_nsegs++; 558 } 559 if ((resv_last > first) && (resv_last < last)) { 560 u_quad_t new_first; 561 562 /* 563 * reserved end in segment 564 * salvage the trailing fragment 565 */ 566 resv_flag = 1; 567 new_first = first + (resv_last - first); 568 KASSERT (last > (new_first + NBPG)); 569 new_segs[new_nsegs].start = new_first; 570 new_segs[new_nsegs].size = last - new_first; 571 new_nsegs++; 572 } 573 if (resv_flag == 0) { 574 /* 575 * nothing reserved here, take it all 576 */ 577 new_segs[new_nsegs].start = first; 578 new_segs[new_nsegs].size = last - first; 579 new_nsegs++; 580 } 581 582 } 583 584 memcpy(segs, new_segs, sizeof(new_segs)); 585 586 return new_nsegs; 587 } 588 589 /* 590 * create an extent for physical address space 591 * these are in units of MB for sake of compression (for sake of 32 bit kernels) 592 * allocate the regions where we have known functions (DRAM, IO, etc) 593 * what remains can be allocated as needed for other stuff 594 * e.g. to configure BARs that are not already initialized and enabled. 595 */ 596 static void 597 rmixl_physaddr_init(void) 598 { 599 struct extent *ext; 600 unsigned long start = 0UL; 601 unsigned long end = (__BIT(40) / (1024 * 1024)) -1; 602 u_long base; 603 u_long size; 604 uint32_t r; 605 606 ext = extent_create("physaddr", start, end, 607 (void *)rmixl_physaddr_storage, sizeof(rmixl_physaddr_storage), 608 EX_NOWAIT | EX_NOCOALESCE); 609 610 if (ext == NULL) 611 panic("%s: extent_create failed", __func__); 612 613 /* 614 * grab regions per DRAM BARs 615 */ 616 for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) { 617 r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i)); 618 if ((r & RMIXL_DRAM_BAR_STATUS) == 0) 619 continue; /* not enabled */ 620 base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024)); 621 size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024)); 622 623 DPRINTF(("%s: %d: %d: 0x%08x -- 0x%010lx:%lu MB\n", 624 __func__, __LINE__, i, r, base * (1024 * 1024), size)); 625 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0) 626 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) " 627 "failed", __func__, ext, base, size, EX_NOWAIT); 628 } 629 630 /* 631 * get chip-dependent physaddr regions 632 */ 633 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 634 case CIDFL_RMI_TYPE_XLR: 635 #if NRMIXL_PCIX 636 rmixl_physaddr_init_pcix(ext); 637 #endif 638 break; 639 case CIDFL_RMI_TYPE_XLS: 640 #if NRMIXL_PCIE 641 rmixl_physaddr_init_pcie(ext); 642 #endif 643 break; 644 case CIDFL_RMI_TYPE_XLP: 645 /* XXX TBD */ 646 panic("%s: RMI XLP not yet supported", __func__); 647 } 648 649 /* 650 * at this point all regions left in "physaddr" extent 651 * are unused holes in the physical address space 652 * available for use as needed. 653 */ 654 rmixl_configuration.rc_phys_ex = ext; 655 #ifdef MACHDEP_DEBUG 656 extent_print(ext); 657 #endif 658 } 659 660 static uint64_t 661 rmixlfw_init(int64_t infop) 662 { 663 struct rmixl_config *rcp = &rmixl_configuration; 664 665 #ifdef MULTIPROCESSOR 666 rmixl_get_wakeup_info(rcp); 667 #endif 668 669 infop |= MIPS_KSEG0_START; 670 rcp->rc_psb_info = *(rmixlfw_info_t *)(intptr_t)infop; 671 672 rcp->rc_psb_type = PSB_TYPE_UNKNOWN; 673 for (int i=0; i < RMICLFW_PSB_VERSIONS_LEN; i++) { 674 if (rmiclfw_psb_id[i].psb_version == 675 rcp->rc_psb_info.psb_version) { 676 rcp->rc_psb_type = rmiclfw_psb_id[i].psb_type; 677 goto found; 678 } 679 } 680 681 rcp->rc_io_pbase = RMIXL_IO_DEV_PBASE; 682 rmixl_putchar_init(rcp->rc_io_pbase); 683 684 #ifdef DIAGNOSTIC 685 rmixl_puts("\r\nWARNING: untested psb_version: "); 686 rmixl_puthex64(rcp->rc_psb_info.psb_version); 687 rmixl_puts("\r\n"); 688 #endif 689 690 #ifdef MEMSIZE 691 /* XXX trust and use MEMSIZE */ 692 mem_clusters[0].start = 0; 693 mem_clusters[0].size = MEMSIZE; 694 mem_cluster_cnt = 1; 695 return MEMSIZE; 696 #else 697 rmixl_puts("\r\nERROR: configure MEMSIZE\r\n"); 698 cpu_reboot(RB_HALT, NULL); 699 /* NOTREACHED */ 700 #endif 701 702 found: 703 rcp->rc_io_pbase = MIPS_KSEG1_TO_PHYS(rcp->rc_psb_info.io_base); 704 rmixl_putchar_init(rcp->rc_io_pbase); 705 #ifdef MACHDEP_DEBUG 706 rmixl_puts("\r\ninfop: "); 707 rmixl_puthex64((uint64_t)(intptr_t)infop); 708 #endif 709 #ifdef DIAGNOSTIC 710 rmixl_puts("\r\nrecognized psb_version="); 711 rmixl_puthex64(rcp->rc_psb_info.psb_version); 712 rmixl_puts(", psb_type="); 713 rmixl_puts(rmixlfw_psb_type_name(rcp->rc_psb_type)); 714 rmixl_puts("\r\n"); 715 #endif 716 717 return mem_clusters_init( 718 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.psb_physaddr_map, 719 (rmixlfw_mmap_t *)(intptr_t)rcp->rc_psb_info.avail_mem_map); 720 } 721 722 void 723 rmixlfw_mmap_print(rmixlfw_mmap_t *map) 724 { 725 #ifdef MACHDEP_DEBUG 726 for (uint32_t i=0; i < map->nmmaps; i++) { 727 rmixl_puthex32(i); 728 rmixl_puts(", "); 729 rmixl_puthex64(map->entry[i].start); 730 rmixl_puts(", "); 731 rmixl_puthex64(map->entry[i].size); 732 rmixl_puts(", "); 733 rmixl_puthex32(map->entry[i].type); 734 rmixl_puts("\r\n"); 735 } 736 #endif 737 } 738 739 /* 740 * mem_clusters_init 741 * 742 * initialize mem_clusters[] table based on memory address mapping 743 * provided by boot firmware. 744 * 745 * prefer avail_mem_map if we can, otherwise use psb_physaddr_map. 746 * these will be limited by MEMSIZE if it is configured. 747 * if neither are available, just use MEMSIZE. 748 */ 749 static uint64_t 750 mem_clusters_init( 751 rmixlfw_mmap_t *psb_physaddr_map, 752 rmixlfw_mmap_t *avail_mem_map) 753 { 754 rmixlfw_mmap_t *map = NULL; 755 const char *mapname; 756 uint64_t sz; 757 uint64_t sum; 758 u_int cnt; 759 #ifdef MEMSIZE 760 uint64_t memsize = MEMSIZE; 761 #endif 762 763 #ifdef MACHDEP_DEBUG 764 rmixl_puts("psb_physaddr_map: "); 765 rmixl_puthex64((uint64_t)(intptr_t)psb_physaddr_map); 766 rmixl_puts("\r\n"); 767 #endif 768 if (psb_physaddr_map != NULL) { 769 map = psb_physaddr_map; 770 mapname = "psb_physaddr_map"; 771 rmixlfw_mmap_print(map); 772 } 773 #ifdef DIAGNOSTIC 774 else { 775 rmixl_puts("WARNING: no psb_physaddr_map\r\n"); 776 } 777 #endif 778 779 #ifdef MACHDEP_DEBUG 780 rmixl_puts("avail_mem_map: "); 781 rmixl_puthex64((uint64_t)(intptr_t)avail_mem_map); 782 rmixl_puts("\r\n"); 783 #endif 784 if (avail_mem_map != NULL) { 785 map = avail_mem_map; 786 mapname = "avail_mem_map"; 787 rmixlfw_mmap_print(map); 788 } 789 #ifdef DIAGNOSTIC 790 else { 791 rmixl_puts("WARNING: no avail_mem_map\r\n"); 792 } 793 #endif 794 795 if (map == NULL) { 796 #ifndef MEMSIZE 797 rmixl_puts("panic: no firmware memory map, " 798 "must configure MEMSIZE\r\n"); 799 for(;;); /* XXX */ 800 #else 801 #ifdef DIAGNOSTIC 802 rmixl_puts("WARNING: no avail_mem_map, " 803 "using MEMSIZE\r\n"); 804 #endif 805 806 mem_clusters[0].start = 0; 807 mem_clusters[0].size = MEMSIZE; 808 mem_cluster_cnt = 1; 809 return MEMSIZE; 810 #endif /* MEMSIZE */ 811 } 812 813 #ifdef DIAGNOSTIC 814 rmixl_puts("using "); 815 rmixl_puts(mapname); 816 rmixl_puts("\r\n"); 817 #endif 818 #ifdef MACHDEP_DEBUG 819 rmixl_puts("memory clusters:\r\n"); 820 #endif 821 sum = 0; 822 cnt = 0; 823 for (uint32_t i=0; i < map->nmmaps; i++) { 824 if (map->entry[i].type != RMIXLFW_MMAP_TYPE_RAM) 825 continue; 826 mem_clusters[cnt].start = map->entry[i].start; 827 sz = map->entry[i].size; 828 sum += sz; 829 mem_clusters[cnt].size = sz; 830 #ifdef MACHDEP_DEBUG 831 rmixl_puthex32(i); 832 rmixl_puts(": "); 833 rmixl_puthex64(mem_clusters[cnt].start); 834 rmixl_puts(", "); 835 rmixl_puthex64(sz); 836 rmixl_puts(": "); 837 rmixl_puthex64(sum); 838 rmixl_puts("\r\n"); 839 #endif 840 #ifdef MEMSIZE 841 /* 842 * configurably limit memsize 843 */ 844 if (sum == memsize) 845 break; 846 if (sum > memsize) { 847 uint64_t tmp; 848 849 tmp = sum - memsize; 850 sz -= tmp; 851 sum -= tmp; 852 mem_clusters[cnt].size = sz; 853 cnt++; 854 break; 855 } 856 #endif 857 cnt++; 858 } 859 mem_cluster_cnt = cnt; 860 return sum; 861 } 862 863 #ifdef MULTIPROCESSOR 864 /* 865 * RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7 866 * they do not explicitly give us the size of the wakeup area. 867 * we "know" that firmware loader sets wip->gp thusly: 868 * gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2)) 869 * so 870 * round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2)) 871 * Only the "master" cpu runs this function, so 872 * vcpu = wip->master_cpu 873 */ 874 void 875 rmixl_get_wakeup_info(struct rmixl_config *rcp) 876 { 877 volatile rmixlfw_cpu_wakeup_info_t *wip; 878 int32_t scratch_7; 879 intptr_t end; 880 881 __asm__ volatile( 882 ".set push" "\n" 883 ".set noreorder" "\n" 884 ".set mips64" "\n" 885 "dmfc0 %0, $22, 7" "\n" 886 ".set pop" "\n" 887 : "=r"(scratch_7)); 888 889 wip = (volatile rmixlfw_cpu_wakeup_info_t *) 890 (intptr_t)scratch_7; 891 end = wip->entry.gp - (wip->master_cpu & (PAGE_SIZE * 2)); 892 893 if (wip->valid == 1) { 894 rcp->rc_cpu_wakeup_end = (const void *)end; 895 rcp->rc_cpu_wakeup_info = wip; 896 } 897 }; 898 899 #ifdef MACHDEP_DEBUG 900 static void 901 rmixl_wakeup_info_print(volatile rmixlfw_cpu_wakeup_info_t *wip) 902 { 903 int i; 904 905 printf("%s: wip %p, size %lu\n", __func__, wip, sizeof(*wip)); 906 907 printf("cpu_status %#x\n", wip->cpu_status); 908 printf("valid: %d\n", wip->valid); 909 printf("entry: addr %#x, args %#x, sp %#"PRIx64", gp %#"PRIx64"\n", 910 wip->entry.addr, 911 wip->entry.args, 912 wip->entry.sp, 913 wip->entry.gp); 914 printf("master_cpu %d\n", wip->master_cpu); 915 printf("master_cpu_mask %#x\n", wip->master_cpu_mask); 916 printf("buddy_cpu_mask %#x\n", wip->buddy_cpu_mask); 917 printf("psb_os_cpu_map %#x\n", wip->psb_os_cpu_map); 918 printf("argc %d\n", wip->argc); 919 printf("argv:"); 920 for (i=0; i < wip->argc; i++) 921 printf(" %#x", wip->argv[i]); 922 printf("\n"); 923 printf("valid_tlb_entries %d\n", wip->valid_tlb_entries); 924 printf("tlb_map:\n"); 925 for (i=0; i < wip->valid_tlb_entries; i++) { 926 volatile const struct lib_cpu_tlb_mapping *m = 927 &wip->tlb_map[i]; 928 printf(" %d", m->page_size); 929 printf(", %d", m->asid); 930 printf(", %d", m->coherency); 931 printf(", %d", m->coherency); 932 printf(", %d", m->attr); 933 printf(", %#x", m->virt); 934 printf(", %#"PRIx64"\n", m->phys); 935 } 936 printf("elf segs:\n"); 937 for (i=0; i < MAX_ELF_SEGMENTS; i++) { 938 volatile const struct core_segment_info *e = 939 &wip->seg_info[i]; 940 printf(" %#"PRIx64"", e->vaddr); 941 printf(", %#"PRIx64"", e->memsz); 942 printf(", %#x\n", e->flags); 943 } 944 printf("envc %d\n", wip->envc); 945 for (i=0; i < wip->envc; i++) 946 printf(" %#x \"%s\"", wip->envs[i], 947 (char *)(intptr_t)(int32_t)(wip->envs[i])); 948 printf("\n"); 949 printf("app_mode %d\n", wip->app_mode); 950 printf("printk_lock %#x\n", wip->printk_lock); 951 printf("kseg_master %d\n", wip->kseg_master); 952 printf("kuseg_reentry_function %#x\n", wip->kuseg_reentry_function); 953 printf("kuseg_reentry_args %#x\n", wip->kuseg_reentry_args); 954 printf("app_shared_mem_addr %#"PRIx64"\n", wip->app_shared_mem_addr); 955 printf("app_shared_mem_size %#"PRIx64"\n", wip->app_shared_mem_size); 956 printf("app_shared_mem_orig %#"PRIx64"\n", wip->app_shared_mem_orig); 957 printf("loader_lock %#x\n", wip->loader_lock); 958 printf("global_wakeup_mask %#x\n", wip->global_wakeup_mask); 959 printf("unused_0 %#x\n", wip->unused_0); 960 } 961 #endif /* MACHDEP_DEBUG */ 962 #endif /* MULTIPROCESSOR */ 963 964 void 965 consinit(void) 966 { 967 968 /* 969 * Everything related to console initialization is done 970 * in mach_init(). 971 */ 972 } 973 974 /* 975 * Allocate memory for variable-sized tables, 976 */ 977 void 978 cpu_startup(void) 979 { 980 /* 981 * Virtual memory is bootstrapped -- notify the bus spaces 982 * that memory allocation is now safe. 983 */ 984 rmixl_configuration.rc_mallocsafe = 1; 985 986 /* Do the usual stuff */ 987 cpu_startup_common(); 988 } 989 990 int waittime = -1; 991 992 void 993 cpu_reboot(int howto, char *bootstr) 994 { 995 996 /* Take a snapshot before clobbering any registers. */ 997 savectx(lwp_getpcb(curlwp)); 998 999 if (cold) { 1000 howto |= RB_HALT; 1001 goto haltsys; 1002 } 1003 1004 /* If "always halt" was specified as a boot flag, obey. */ 1005 if (boothowto & RB_HALT) 1006 howto |= RB_HALT; 1007 1008 boothowto = howto; 1009 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 1010 waittime = 0; 1011 vfs_shutdown(); 1012 1013 /* 1014 * If we've been adjusting the clock, the todr 1015 * will be out of synch; adjust it now. 1016 */ 1017 resettodr(); 1018 } 1019 1020 splhigh(); 1021 1022 if (howto & RB_DUMP) 1023 dumpsys(); 1024 1025 haltsys: 1026 doshutdownhooks(); 1027 1028 if (howto & RB_HALT) { 1029 printf("\n"); 1030 printf("The operating system has halted.\n"); 1031 printf("Please press any key to reboot.\n\n"); 1032 cnpollc(1); /* For proper keyboard command handling */ 1033 cngetc(); 1034 cnpollc(0); 1035 } 1036 1037 printf("rebooting...\n\n"); 1038 1039 rmixl_reset(); 1040 } 1041 1042 /* 1043 * goodbye world 1044 */ 1045 void __attribute__((__noreturn__)) 1046 rmixl_reset(void) 1047 { 1048 uint32_t r; 1049 1050 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET); 1051 r |= RMIXL_GPIO_RESET_RESET; 1052 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET, r); 1053 1054 printf("soft reset failed, spinning...\n"); 1055 for (;;); 1056 } 1057