1 /* $OpenBSD: isa_machdep.c,v 1.1 2010/05/08 21:59:56 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Legacy device support. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 27 #include <evbmips/loongson/autoconf.h> 28 #include <machine/intr.h> 29 30 #include <dev/ic/i8259reg.h> 31 32 #include <dev/pci/pcivar.h> 33 34 #include <dev/isa/isareg.h> 35 #include <dev/isa/isavar.h> 36 37 #include <mips/bonito/bonitoreg.h> 38 #include <mips/bonito/bonitovar.h> 39 40 #include <evbmips/loongson/loongson_isa.h> 41 42 uint loongson_isaimr; 43 44 void 45 loongson_set_isa_imr(uint newimr) 46 { 47 uint imr1, imr2; 48 49 imr1 = 0xff & ~newimr; 50 imr1 &= ~(1 << 2); /* enable cascade */ 51 imr2 = 0xff & ~(newimr >> 8); 52 53 /* 54 * For some reason, trying to write the same value to the PIC 55 * registers causes an immediate system freeze (at least on the 56 * 2F and CS5536 based Lemote Yeeloong), so we only do this if 57 * the value changes. 58 * Note that interrupts have been disabled by the caller. 59 */ 60 //if ((newimr ^ loongson_isaimr) & 0xff00) 61 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = imr2; 62 //if ((newimr ^ loongson_isaimr) & 0x00ff) 63 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) = imr1; 64 __asm__ __volatile__ ("sync" ::: "memory"); 65 loongson_isaimr = newimr; 66 } 67 68 void 69 loongson_isa_specific_eoi(int bit) 70 { 71 KASSERT((bit < 16) && (bit >= 0)); 72 loongson_isaimr &= ~(1 << bit); 73 if (bit & 8) { 74 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1); 75 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + 1) = 76 (0xff & ~(loongson_isaimr >> 8)); 77 __asm__ __volatile__ ("sync" ::: "memory"); 78 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW2) = 79 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(bit & 7); 80 bit = 2; 81 __asm__ __volatile__ ("sync" ::: "memory"); 82 } 83 (void)REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1); 84 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + 1) = 85 (0xff & ~(loongson_isaimr)); 86 __asm__ __volatile__ ("sync" ::: "memory"); 87 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW2) = 88 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(bit); 89 __asm__ __volatile__ ("sync" ::: "memory"); 90 } 91