1/* $NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "opt_cputype.h" 30#include "opt_multiprocessor.h" 31 32#include <sys/cdefs.h> 33#include <sys/endian.h> 34 35#include <mips/asm.h> 36RCSID("$NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $"); 37 38#ifdef MULTIPROCESSOR 39 40#include <mips/cpuregs.h> 41#include <mips/cache_r4k.h> 42 43#include "assym.h" 44 45#define CACHE_SIZE (32 * 1024) 46#define CACHE_LINESIZE 32 47 48NESTED_NOPROFILE(ingenic_trampoline, 0, ra) 49 /* 50 * We act as the idle lwp so make it CURLWP. When know 51 * that the cpu_info is a KSEG0 address. 52 */ 53 move a0, a1 54 // Loop until idlelwp is filled in. 551: PTR_L MIPS_CURLWP, CPU_INFO_IDLELWP(a0) 56 nop 57 beqz MIPS_CURLWP, 1b 58 nop 59 PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(a0) 60 61 li v0, 0 62 mtc0 v0, MIPS_COP_0_STATUS # reset to known state 63 COP0_SYNC 64 65 PTR_L sp, L_MD_UTF(MIPS_CURLWP) # fetch KSP 66 67 /* 68 * Indicate that no one has called us. 69 */ 70 move ra, zero 71 REG_S ra, CALLFRAME_RA(sp) 72 73 /* 74 * New execution constant needs GP to be loaded. 75 */ 76 PTR_LA gp, _C_LABEL(_gp) 77 78 /* 79 * and off we go. 80 */ 81 j _C_LABEL(cpu_hatch) # does everything 82 nop 83END(ingenic_trampoline) 84 85 86/* 87 * exception vector secondary CPUs take when started 88 */ 89.p2align 16 90VECTOR(ingenic_wakeup, unknown) 91 .set noat 92 93 mtc0 zero, MIPS_COP_0_CAUSE 94 COP0_SYNC 95 96 /* init caches */ 97 li t0, MIPS_KSEG0_START 98 ori t1, t0, CACHE_SIZE 99 mtc0 zero, MIPS_COP_0_TAG_LO, 0 100 COP0_SYNC 1011: cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_I, 0(t0) 102 cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0) 103 addiu t0, t0, CACHE_LINESIZE 104 bne t0, t1, 1b 105 nop 106 107 /* kseg0 cache attribute */ 108 mfc0 t0, MIPS_COP_0_CONFIG, 0 109 ori t0, t0, MIPS3_TLB_ATTR_WB_NONCOHERENT 110 mtc0 t0, MIPS_COP_0_CONFIG, 0 111 COP0_SYNC 112 113 /* pagemask */ 114 mtc0 zero, MIPS_COP_0_TLB_PG_MASK, 0 115 COP0_SYNC 116 117 /* 118 * - set a1 to corresponding cpu_info 119 * - set sp to ci->ci_data.cpu_idlelwp->l_md.md_utf 120 * - jump to cpu_trampoline 121 */ 122 PTR_L a1, _C_LABEL(startup_cpu_info) 123 nop 124 125 j ingenic_trampoline 126 nop 127 .set at 128VECTOR_END(ingenic_wakeup) 129 130#endif /* MULTIPROCESSOR */ 131