1 /* $NetBSD: cpu.c,v 1.5 2022/03/03 06:27:40 riastradh Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.5 2022/03/03 06:27:40 riastradh Exp $"); 40 41 #include "opt_ingenic.h" 42 #include "opt_multiprocessor.h" 43 44 #include <sys/param.h> 45 #include <sys/device.h> 46 #include <sys/systm.h> 47 #include <sys/cpu.h> 48 49 #include <mips/locore.h> 50 #include <mips/ingenic/ingenic_coreregs.h> 51 #include <mips/ingenic/ingenic_regs.h> 52 #include <mips/ingenic/ingenic_var.h> 53 54 static int cpu_match(device_t, cfdata_t, void *); 55 static void cpu_attach(device_t, device_t, void *); 56 57 CFATTACH_DECL_NEW(cpu, 0, 58 cpu_match, cpu_attach, NULL, NULL); 59 60 struct cpu_info *startup_cpu_info; 61 extern void *ingenic_wakeup; 62 63 static int 64 cpu_match(device_t parent, cfdata_t match, void *aux) 65 { 66 struct mainbusdev { 67 const char *md_name; 68 } *aa = aux; 69 if (strcmp(aa->md_name, "cpu") == 0) return 1; 70 return 0; 71 } 72 73 static void 74 cpu_attach(device_t parent, device_t self, void *aux) 75 { 76 struct cpu_info *ci = curcpu(); 77 int unit; 78 79 if ((unit = device_unit(self)) > 0) { 80 #ifdef MULTIPROCESSOR 81 uint32_t vec, reg; 82 int bail = 10000; 83 84 startup_cpu_info = cpu_info_alloc(NULL, unit, 0, unit, 0); 85 startup_cpu_info->ci_cpu_freq = ci->ci_cpu_freq; 86 ci = startup_cpu_info; 87 wbflush(); 88 vec = (uint32_t)&ingenic_wakeup; 89 reg = mips_cp0_corereim_read(); 90 reg &= ~REIM_ENTRY_M; 91 reg |= vec; 92 mips_cp0_corereim_write(reg); 93 94 reg = mips_cp0_corectrl_read(); 95 reg |= CC_RPC1; /* use our exception vector */ 96 reg &= ~CC_SW_RST1; /* get core 1 out of reset */ 97 mips_cp0_corectrl_write(reg); 98 99 while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) { 100 delay(1000); 101 bail--; 102 } 103 if (!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) { 104 aprint_error_dev(self, "did not hatch\n"); 105 return; 106 } 107 #else 108 aprint_normal_dev(self, 109 "processor off-line; " 110 "multiprocessor support not present in kernel\n"); 111 return; 112 #endif 113 114 } 115 ci->ci_dev = self; 116 device_set_private(self, ci); 117 118 aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n", 119 ci->ci_cpu_freq / 1000000, 120 (ci->ci_cpu_freq % 1000000) / 10000, 121 ci->ci_cycles_per_hz, ci->ci_divisor_delay); 122 123 aprint_normal_dev(self, ""); 124 cpu_identify(self); 125 cpu_attach_common(self, ci); 126 } 127