1 /* $NetBSD: intr.h,v 1.14 2007/12/03 15:33:33 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _EVBMIPS_INTR_H_ 40 #define _EVBMIPS_INTR_H_ 41 42 #include <sys/device.h> 43 #include <sys/lock.h> 44 #include <sys/queue.h> 45 46 #define IPL_NONE 0 /* disable only this interrupt */ 47 #define IPL_SOFTCLOCK 1 /* software interrupts */ 48 #define IPL_SOFTBIO 1 /* software interrupts */ 49 #define IPL_SOFTNET 2 /* software interrupts */ 50 #define IPL_SOFTSERIAL 2 /* software interrupts */ 51 #define IPL_VM 3 52 #define IPL_SCHED 4 53 #define IPL_HIGH 4 54 55 #define _IPL_N 5 /* max IPL + 1 */ 56 57 #define _IPL_SI0_FIRST IPL_SOFTCLOCK 58 #define _IPL_SI0_LAST IPL_SOFTBIO 59 60 #define _IPL_SI1_FIRST IPL_SOFTNET 61 #define _IPL_SI1_LAST IPL_SOFTSERIAL 62 63 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 64 #define IST_NONE 0 /* none (dummy) */ 65 #define IST_PULSE 1 /* pulsed */ 66 #define IST_EDGE 2 /* edge-triggered */ 67 #define IST_LEVEL 3 /* level-triggered */ 68 #define IST_LEVEL_HIGH 4 /* level triggered, active high */ 69 #define IST_LEVEL_LOW 5 /* level triggered, active low */ 70 71 #ifdef _KERNEL 72 73 #include <mips/locore.h> 74 75 extern const uint32_t ipl_sr_bits[_IPL_N]; 76 77 #define spl0() (void) _spllower(0) 78 #define splx(s) (void) _splset(s) 79 80 #define splsoft() _splraise(ipl_sr_bits[IPL_SOFT]) 81 82 typedef int ipl_t; 83 typedef struct { 84 ipl_t _sr; 85 } ipl_cookie_t; 86 87 static inline ipl_cookie_t 88 makeiplcookie(ipl_t ipl) 89 { 90 91 return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]}; 92 } 93 94 static inline int 95 splraiseipl(ipl_cookie_t icookie) 96 { 97 98 return _splraise(icookie._sr); 99 } 100 101 #include <sys/spl.h> 102 103 struct evbmips_intrhand { 104 LIST_ENTRY(evbmips_intrhand) ih_q; 105 int (*ih_func)(void *); 106 void *ih_arg; 107 int ih_irq; 108 }; 109 110 #include <mips/softintr.h> 111 112 void evbmips_intr_init(void); 113 void intr_init(void); 114 void evbmips_iointr(uint32_t, uint32_t, uint32_t, uint32_t); 115 void *evbmips_intr_establish(int, int (*)(void *), void *); 116 void evbmips_intr_disestablish(void *); 117 #endif /* _KERNEL */ 118 #endif /* ! _EVBMIPS_INTR_H_ */ 119