1 /* $NetBSD: gdium_intr.c,v 1.5 2011/07/10 00:03:53 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Platform-specific interrupt support for the Algorithmics P-6032. 34 * 35 * The Algorithmics P-6032's interrupts are wired to GPIO pins 36 * on the BONITO system controller. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.5 2011/07/10 00:03:53 matt Exp $"); 41 42 #define __INTR_PRIVATE 43 44 45 #include "opt_ddb.h" 46 47 #include <sys/param.h> 48 #include <sys/bus.h> 49 #include <sys/cpu.h> 50 #include <sys/device.h> 51 #include <sys/intr.h> 52 #include <sys/kernel.h> 53 #include <sys/malloc.h> 54 #include <sys/systm.h> 55 56 #include <mips/locore.h> 57 58 #include <mips/bonito/bonitoreg.h> 59 #include <evbmips/gdium/gdiumvar.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 64 /* 65 * The GDIUM interrupts are wired up in the following way: 66 * 67 * GPIN0 ISA_NMI (in) 68 * GPIN1 ISA_INTR (in) 69 * GPIN2 ETH_INT~ (in) 70 * GPIN3 BONIDE_INT (in) 71 * 72 * PCI_INTA 73 * GPIN4 ISA IRQ3 (in, also on piix4) 74 * GPIN5 ISA IRQ4 (in, also on piix4) 75 * 76 * GPIO0 PIRQ A~ (in) 77 * GPIO1 PIRQ B~ (in) 78 * GPIO2 PIRQ C~ (in) 79 * GPIO3 PIRQ D~ (in) 80 */ 81 82 struct gdium_irqmap { 83 const char *name; 84 uint8_t irqidx; 85 uint8_t flags; 86 }; 87 88 #define IRQ_F_INVERT 0x80 /* invert polarity */ 89 #define IRQ_F_EDGE 0x40 /* edge trigger */ 90 #define IRQ_F_INT0 0x00 /* INT0 */ 91 #define IRQ_F_INT1 0x01 /* INT1 */ 92 #define IRQ_F_INT2 0x02 /* INT2 */ 93 #define IRQ_F_INT3 0x03 /* INT3 */ 94 #define IRQ_F_INTMASK 0x07 /* INT mask */ 95 96 const struct gdium_irqmap gdium_irqmap[] = { 97 { "gpio0", GDIUM_IRQ_GPIO0, IRQ_F_INT0 }, 98 { "gpio1", GDIUM_IRQ_GPIO1, IRQ_F_INT0 }, 99 { "gpio2", GDIUM_IRQ_GPIO2, IRQ_F_INT0 }, 100 { "gpio3", GDIUM_IRQ_GPIO3, IRQ_F_INT0 }, 101 102 { "pci inta", GDIUM_IRQ_PCI_INTA, IRQ_F_INT0 }, 103 { "pci intb", GDIUM_IRQ_PCI_INTB, IRQ_F_INT0 }, 104 { "pci intc", GDIUM_IRQ_PCI_INTC, IRQ_F_INT0 }, 105 { "pci intd", GDIUM_IRQ_PCI_INTD, IRQ_F_INT0 }, 106 107 { "pci perr", GDIUM_IRQ_PCI_PERR, IRQ_F_EDGE|IRQ_F_INT1 }, 108 { "pci serr", GDIUM_IRQ_PCI_SERR, IRQ_F_EDGE|IRQ_F_INT1 }, 109 110 { "denali", GDIUM_IRQ_DENALI, IRQ_F_INT1 }, 111 112 { "mips int0", GDIUM_IRQ_INT0, IRQ_F_INT0 }, 113 { "mips int1", GDIUM_IRQ_INT1, IRQ_F_INT1 }, 114 { "mips int2", GDIUM_IRQ_INT2, IRQ_F_INT2 }, 115 { "mips int3", GDIUM_IRQ_INT3, IRQ_F_INT3 }, 116 }; 117 118 struct gdium_intrhead { 119 struct evcnt intr_count; 120 int intr_refcnt; 121 }; 122 struct gdium_intrhead gdium_intrtab[__arraycount(gdium_irqmap)]; 123 124 #define NINTRS 2 /* MIPS INT0 - INT1 */ 125 126 struct gdium_cpuintr { 127 LIST_HEAD(, evbmips_intrhand) cintr_list; 128 struct evcnt cintr_count; 129 int cintr_refcnt; 130 }; 131 132 struct gdium_cpuintr gdium_cpuintrs[NINTRS]; 133 const char * const gdium_cpuintrnames[NINTRS] = { 134 "int 0 (pci)", 135 "int 1 (errors)", 136 }; 137 138 /* 139 * This is a mask of bits to clear in the SR when we go to a 140 * given hardware interrupt priority level. 141 */ 142 static const struct ipl_sr_map gdium_ipl_sr_map = { 143 .sr_bits = { 144 [IPL_NONE] = 0, 145 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 146 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 147 [IPL_VM] = 148 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 149 MIPS_INT_MASK_0 | 150 MIPS_INT_MASK_1 | 151 MIPS_INT_MASK_2 | 152 MIPS_INT_MASK_3 | 153 MIPS_INT_MASK_4, 154 [IPL_SCHED] = 155 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 156 MIPS_INT_MASK_0 | 157 MIPS_INT_MASK_1 | 158 MIPS_INT_MASK_2 | 159 MIPS_INT_MASK_3 | 160 MIPS_INT_MASK_4 | 161 MIPS_INT_MASK_5, 162 [IPL_DDB] = MIPS_INT_MASK, 163 [IPL_HIGH] = MIPS_INT_MASK, 164 }, 165 }; 166 167 int gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 168 const char *gdium_pci_intr_string(void *, pci_intr_handle_t); 169 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t); 170 void *gdium_pci_intr_establish(void *, pci_intr_handle_t, int, 171 int (*)(void *), void *); 172 void gdium_pci_intr_disestablish(void *, void *); 173 void gdium_pci_conf_interrupt(void *, int, int, int, int, int *); 174 175 void 176 evbmips_intr_init(void) 177 { 178 struct gdium_config * const gc = &gdium_configuration; 179 struct bonito_config *bc = &gc->gc_bonito; 180 const struct gdium_irqmap *irqmap; 181 uint32_t intbit; 182 size_t i; 183 184 ipl_sr_map = gdium_ipl_sr_map; 185 186 for (i = 0; i < NINTRS; i++) { 187 LIST_INIT(&gdium_cpuintrs[i].cintr_list); 188 evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count, 189 EVCNT_TYPE_INTR, NULL, "mips", gdium_cpuintrnames[i]); 190 } 191 //evcnt_attach_static(&mips_int5_evcnt); 192 193 for (i = 0; i < __arraycount(gdium_irqmap); i++) { 194 irqmap = &gdium_irqmap[i]; 195 intbit = 1 << irqmap->irqidx; 196 197 evcnt_attach_dynamic(&gdium_intrtab[i].intr_count, 198 EVCNT_TYPE_INTR, NULL, "bonito", irqmap->name); 199 200 if (irqmap->irqidx < 4) 201 bc->bc_gpioIE |= intbit; 202 if (irqmap->flags & IRQ_F_INVERT) 203 bc->bc_intPol |= intbit; 204 if (irqmap->flags & IRQ_F_EDGE) 205 bc->bc_intEdge |= intbit; 206 if ((irqmap->flags & IRQ_F_INTMASK) == IRQ_F_INT1) 207 bc->bc_intSteer |= intbit; 208 209 REGVAL(BONITO_INTENCLR) = intbit; 210 } 211 212 REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE; 213 REGVAL(BONITO_INTEDGE) = bc->bc_intEdge; 214 REGVAL(BONITO_INTSTEER) = bc->bc_intSteer; 215 REGVAL(BONITO_INTPOL) = bc->bc_intPol; 216 217 gc->gc_pc.pc_intr_v = NULL; 218 gc->gc_pc.pc_intr_map = gdium_pci_intr_map; 219 gc->gc_pc.pc_intr_string = gdium_pci_intr_string; 220 gc->gc_pc.pc_intr_evcnt = gdium_pci_intr_evcnt; 221 gc->gc_pc.pc_intr_establish = gdium_pci_intr_establish; 222 gc->gc_pc.pc_intr_disestablish = gdium_pci_intr_disestablish; 223 gc->gc_pc.pc_conf_interrupt = gdium_pci_conf_interrupt; 224 225 /* We let the PCI-ISA bridge code handle this. */ 226 gc->gc_pc.pc_pciide_compat_intr_establish = NULL; 227 } 228 229 void * 230 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 231 { 232 const struct gdium_irqmap *irqmap; 233 struct evbmips_intrhand *ih; 234 int level; 235 int s; 236 237 irqmap = &gdium_irqmap[irq]; 238 KASSERT(irq < __arraycount(gdium_irqmap)); 239 240 KASSERT(irq == irqmap->irqidx); 241 242 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT|M_ZERO); 243 if (ih == NULL) 244 return NULL; 245 246 ih->ih_func = func; 247 ih->ih_arg = arg; 248 ih->ih_irq = irq; 249 250 s = splhigh(); 251 252 /* 253 * First, link it into the tables. 254 */ 255 level = (irqmap->flags & IRQ_F_INT1) != 0; 256 LIST_INSERT_HEAD(&gdium_cpuintrs[level].cintr_list, ih, ih_q); 257 gdium_cpuintrs[level].cintr_refcnt++; 258 259 /* 260 * Now enable it. 261 */ 262 if (gdium_intrtab[ih->ih_irq].intr_refcnt++ == 0) 263 REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq); 264 265 splx(s); 266 267 return (ih); 268 } 269 270 void 271 evbmips_intr_disestablish(void *cookie) 272 { 273 const struct gdium_irqmap *irqmap; 274 struct evbmips_intrhand *ih = cookie; 275 int s; 276 277 irqmap = &gdium_irqmap[ih->ih_irq]; 278 279 s = splhigh(); 280 281 /* 282 * First, remove it from the table. 283 */ 284 LIST_REMOVE(ih, ih_q); 285 gdium_cpuintrs[(irqmap->flags & IRQ_F_INT1) != 0].cintr_refcnt--; 286 287 /* 288 * Now, disable it, if there is nothing remaining on the 289 * list. 290 */ 291 if (gdium_intrtab[ih->ih_irq].intr_refcnt-- == 1) 292 REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq); 293 294 splx(s); 295 296 free(ih, M_DEVBUF); 297 } 298 299 void 300 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 301 { 302 const struct gdium_irqmap *irqmap; 303 struct evbmips_intrhand *ih; 304 int level; 305 uint32_t isr; 306 307 /* 308 * Read the interrupt pending registers, mask them with the 309 * ones we have enabled, and service them in order of decreasing 310 * priority. 311 */ 312 isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN); 313 for (level = 1; level >= 0; level--) { 314 if ((ipending & (MIPS_INT_MASK_4 << level)) == 0) 315 continue; 316 gdium_cpuintrs[level].cintr_count.ev_count++; 317 LIST_FOREACH (ih, &gdium_cpuintrs[level].cintr_list, ih_q) { 318 irqmap = &gdium_irqmap[ih->ih_irq]; 319 if (isr & (1 << ih->ih_irq)) { 320 gdium_intrtab[ih->ih_irq].intr_count.ev_count++; 321 (*ih->ih_func)(ih->ih_arg); 322 } 323 } 324 } 325 } 326 327 /***************************************************************************** 328 * PCI interrupt support 329 *****************************************************************************/ 330 331 int 332 gdium_pci_intr_map(const struct pci_attach_args *pa, 333 pci_intr_handle_t *ihp) 334 { 335 static const int8_t pciirqmap[5/*device*/] = { 336 GDIUM_IRQ_PCI_INTC, /* 13: PCI 802.11 */ 337 GDIUM_IRQ_PCI_INTA, /* 14: SM501 */ 338 GDIUM_IRQ_PCI_INTB, /* 15: NEC USB (2 func) */ 339 GDIUM_IRQ_PCI_INTD, /* 16: Ethernet */ 340 GDIUM_IRQ_PCI_INTC, /* 17: NEC USB (2 func) */ 341 }; 342 pcitag_t bustag = pa->pa_intrtag; 343 int buspin = pa->pa_intrpin; 344 pci_chipset_tag_t pc = pa->pa_pc; 345 int device; 346 347 if (buspin == 0) { 348 /* No IRQ used. */ 349 return (1); 350 } 351 352 if (buspin > 4) { 353 printf("gdium_pci_intr_map: bad interrupt pin %d\n", 354 buspin); 355 return (1); 356 } 357 358 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 359 if (device < 13 || device > 17) { 360 printf("gdium_pci_intr_map: bad device %d\n", 361 device); 362 return (1); 363 } 364 365 *ihp = pciirqmap[device - 13]; 366 return (0); 367 } 368 369 const char * 370 gdium_pci_intr_string(void *v, pci_intr_handle_t ih) 371 { 372 373 if (ih >= __arraycount(gdium_irqmap)) 374 panic("gdium_intr_string: bogus IRQ %ld", ih); 375 376 return gdium_irqmap[ih].name; 377 } 378 379 const struct evcnt * 380 gdium_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 381 { 382 383 return &gdium_intrtab[ih].intr_count; 384 } 385 386 void * 387 gdium_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 388 int (*func)(void *), void *arg) 389 { 390 391 if (ih >= __arraycount(gdium_irqmap)) 392 panic("gdium_pci_intr_establish: bogus IRQ %ld", ih); 393 394 return evbmips_intr_establish(ih, func, arg); 395 } 396 397 void 398 gdium_pci_intr_disestablish(void *v, void *cookie) 399 { 400 401 return (evbmips_intr_disestablish(cookie)); 402 } 403 404 void 405 gdium_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 406 int *iline) 407 { 408 409 /* 410 * We actually don't need to do anything; everything is handled 411 * in pci_intr_map(). 412 */ 413 *iline = 0; 414 } 415