xref: /netbsd-src/sys/arch/evbmips/alchemy/omsal400.c (revision e6c7e151de239c49d2e38720a061ed9d1fa99309)
1 /* $NetBSD: omsal400.c,v 1.10 2015/06/09 22:49:55 matt Exp $ */
2 
3 /*-
4  * Copyright (c) 2006 Itronix Inc.
5  * Copyright (c) 2006 Shigeyuki Fukushima.
6  * All rights reserved.
7  *
8  * Written by Garrett D'Amore for Itronix Inc
9  * Written by Shigeyuki Fukushima.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above
17  *    copyright notice, this list of conditions and the following
18  *    disclaimer in the documentation and/or other materials provided
19  *    with the distribution.
20  * 3. The name of the author may not be used to endorse or promote
21  *    products derived from this software without specific prior
22  *    written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
25  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
28  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
30  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: omsal400.c,v 1.10 2015/06/09 22:49:55 matt Exp $");
40 
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/cpu.h>
44 
45 #include <mips/locore.h>
46 #include <mips/cpuregs.h>
47 
48 #include <mips/alchemy/dev/augpiovar.h>
49 #include <mips/alchemy/dev/aupcmciavar.h>
50 
51 #include <evbmips/alchemy/obiovar.h>
52 #include <evbmips/alchemy/board.h>
53 #include <evbmips/alchemy/omsal400reg.h>
54 
55 #define	GET16(x)	\
56 	(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
57 #define	PUT16(x, v)	\
58 	(*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
59 
60 static void	omsal400_init(void);
61 static int	omsal400_pci_intr_map(const struct pci_attach_args *,
62 					 pci_intr_handle_t *);
63 static void	omsal400_poweroff(void);
64 static void	omsal400_reboot(void);
65 static bus_addr_t omsal400_slot_offset(int);
66 static int omsal400_slot_irq(int, int);
67 static void omsal400_slot_enable(int);
68 static void omsal400_slot_disable(int);
69 static int omsal400_slot_status(int);
70 static const char *omsal400_slot_name(int);
71 
72 static const struct obiodev omsal400_devices[] = {
73 	{ NULL },
74 };
75 
76 static struct aupcmcia_machdep omsal400_pcmcia = {
77 	1,      /* nslots */
78 	omsal400_slot_offset,
79 	omsal400_slot_irq,
80 	omsal400_slot_enable,
81 	omsal400_slot_disable,
82 	omsal400_slot_status,
83 	omsal400_slot_name,
84 };
85 
86 static struct alchemy_board omsal400_info = {
87 	"Plathome Open Micro Server AL400/AMD Alchemy Au1550",
88 	omsal400_devices,
89 	omsal400_init,
90 	omsal400_pci_intr_map,
91 	omsal400_reboot,
92 	omsal400_poweroff,
93 	&omsal400_pcmcia,
94 };
95 
96 const struct alchemy_board *
97 board_info(void)
98 {
99 
100 	return &omsal400_info;
101 }
102 
103 void
104 omsal400_init(void)
105 {
106 	/* uint16_t whoami; */
107 
108 	if (MIPS_PRID_COPTS(mips_options.mips_cpu_id) != MIPS_AU1550)
109 		panic("omsal400: CPU not Au1550");
110 
111 #if 0 /* XXX: TODO borad identification */
112 	/* check the whoami register for a match */
113 	whoami = GET16(DBAU1550_WHOAMI);
114 
115 	if (DBAU1550_WHOAMI_BOARD(whoami) != DBAU1550_WHOAMI_DBAU1550_REV1)
116 		panic("dbau1550: WHOAMI (%x) not DBAu1550!", whoami);
117 
118 	printf("DBAu1550 (cabernet), CPLDv%d, ",
119 	    DBAU1550_WHOAMI_CPLD(whoami));
120 
121 	if (DBAU1550_WHOAMI_DAUGHTER(whoami) != 0xf)
122 		printf("daughtercard 0x%x\n",
123 		    DBAU1550_WHOAMI_DAUGHTER(whoami));
124 	else
125 		printf("no daughtercard\n");
126 #endif
127 
128 	/* leave console and clocks alone -- YAMON should have got it right! */
129 }
130 
131 int
132 omsal400_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
133 {
134 	/*
135 	 * This platform has 4 PCI devices:
136 	 *  dev 1 (PCI_INTD):	PCI Connector
137 	 *  dev 2 (PCI_INTC):	NEC USB 2.0 uPD720101
138 	 *  dev 3 (PCI_INTB):	Intel GB Ether 82541PI
139 	 *  dev 4 (PCI_INTA):	Intel GB Ether 82541PI
140 	 */
141 	static const int irqmap[4/*device*/][4/*pin*/] = {
142 		{  6, -1, -1, -1 },	/* 1: PCI Connecter (not used) */
143 		{  5,  5,  5, -1 },	/* 2: NEC USB 2.0 */
144 		{  2, -1, -1, -1 },	/* 3: Intel GbE */
145 		{  1, -1, -1, -1 },	/* 4: Intel GbE */
146 	};
147 
148 	int pin, dev, irq;
149 
150 	/* if interrupt pin not used... */
151 	if ((pin = pa->pa_intrpin) == 0)
152 		return 1;
153 
154 	if (pin > 4) {
155 		printf("pci: bad interrupt pin %d\n", pin);
156 		return 1;
157 	}
158 
159 	pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &dev, NULL);
160 
161 	if ((dev < 1) || (dev > 4)) {
162 		printf("pci: bad device %d\n", dev);
163 		return 1;
164 	}
165 
166 	if ((irq = irqmap[dev - 1][pin - 1]) == -1) {
167 		printf("pci: no IRQ routing for device %d pin %d\n", dev, pin);
168 		return 1;
169 	}
170 
171 	*ihp = irq;
172 	return 0;
173 }
174 
175 void
176 omsal400_reboot(void)
177 {
178 
179 	/* XXX */
180 }
181 
182 void
183 omsal400_poweroff(void)
184 {
185 
186 	printf("\n- poweroff -\n");
187 	/* XXX */
188 }
189 
190 
191 int
192 omsal400_slot_irq(int slot, int which)
193 {
194 	static const int irqmap[1/*slot*/][2/*which*/] = {
195 		{ 35, 37 },		/* Slot 0: CF connector Type2 */
196 	};
197 
198 	if ((slot >= 1) || (which >= 2))
199 		return -1;
200 
201 	return irqmap[slot][which];
202 }
203 
204 bus_addr_t
205 omsal400_slot_offset(int slot)
206 {
207 
208 	switch (slot) {
209 	case 0:
210 		return (0);	/* offset 0 */
211 	}
212 	return (bus_addr_t)-1;
213 }
214 
215 void
216 omsal400_slot_enable(int slot)
217 {
218 
219 	/* nothing todo */
220 }
221 
222 void
223 omsal400_slot_disable(int slot)
224 {
225 
226 	/* nothing todo */
227 }
228 
229 int
230 omsal400_slot_status(int slot)
231 {
232 	uint16_t	inserted = 0;
233 
234 	switch (slot) {
235 	case 0:
236 		inserted = !AUGPIO_READ(5);	/* pin 5 */
237 		break;
238 	}
239 
240 	return inserted;
241 }
242 
243 const char *
244 omsal400_slot_name(int slot)
245 {
246 	switch (slot) {
247 	case 0:
248 		return "CF connector Type2 on Static BUS#3";
249 	default:
250 		return "???";
251 	}
252 }
253