1/* $NetBSD: smdk2800_start.S,v 1.7 2005/12/11 12:17:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 2002, 2005 Fujitsu Component Limited 5 * Copyright (c) 2002, 2005 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35#include <machine/asm.h> 36#include <arm/armreg.h> 37#include <arm/arm32/pte.h> 38#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 39 40#include <arm/s3c2xx0/s3c2800reg.h> /* for S3C2800_DBANK0_START */ 41 42#include <evbarm/smdk2xx0/smdk2800var.h> 43 44/* 45 * Kernel start routine for Samsung SMDK2800. 46 * This code is excuted at the very first after the kernel is loaded 47 * by boot program on ROM or gzboot. 48 */ 49 .text 50 51#define KERNEL_TEXT_ADDR (SDRAM_START+0x00200000) 52 53 .global _C_LABEL(smdk2800_start) 54_C_LABEL(smdk2800_start): 55 /* Are we running on right place ? */ 56 adr r0, _C_LABEL(smdk2800_start) 57 cmp r0, #KERNEL_TEXT_ADDR 58 beq smdk2800_start_ram 59 60 /* move me to RAM 61 * XXX: we can use memcpy if it is PIC 62 */ 63 ldr r1, Lcopy_size 64 adr r0, _C_LABEL(smdk2800_start) 65 add r1, r1, #3 66 mov r1, r1, LSR #2 67 mov r2, #KERNEL_TEXT_ADDR 68 mov r4, r2 69 70 cmp r0, r2 71 bhs 5f 72 73 /* src < dest. copy from top */ 74 add r0,r0,r1,LSL #2 75 add r2,r2,r1,LSL #2 76 773: ldr r3,[r0,#-4]! 78 str r3,[r2,#-4]! 79 subs r1,r1,#1 80 bhi 3b 81 b 7f 82 83 /* src >= dest. copy from bottom */ 845: ldr r3,[r0],#4 85 str r3,[r2],#4 86 subs r1,r1,#1 87 bhi 5b 88 897: 90 /* Jump to RAM */ 91 ldr r0, Lstart_off 92 add pc, r4, r0 93 94Lcopy_size: .word _edata-_C_LABEL(smdk2800_start) 95Lstart_off: .word smdk2800_start_ram-_C_LABEL(smdk2800_start) 96 97smdk2800_start_ram: 98 /* 99 * Kernel is loaded in SDRAM (0x08200000..), and is expected to run 100 * in VA 0xc0200000.. 101 */ 102 103 /* Disable MMU for a while */ 104 mrc p15, 0, r2, c1, c0, 0 105 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 106 mcr p15, 0, r2, c1, c0, 0 107 108 nop 109 nop 110 nop 111 112 mov r0,#SDRAM_START /* pagetable */ 113 adr r4, mmu_init_table 114 b 2f 1151: 116 str r3, [r0, r2] 117 add r2, r2, #4 118 add r3, r3, #(L1_S_SIZE) 119 adds r1, r1, #-1 120 bhi 1b 1212: 122 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 123 cmp r1, #0 124 bne 1b 125 126 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 127 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 128 129 /* Set the Domain Access register. Very important! */ 130 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 131 mcr p15, 0, r0, c3, c0, 0 132 133 /* Enable MMU */ 134 mrc p15, 0, r0, c1, c0, 0 135 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 136 mcr p15, 0, r0, c1, c0, 0 137 138 nop 139 nop 140 nop 141 142 /* Jump to kernel code in TRUE VA */ 143 adr r0, Lstart 144 ldr pc, [r0] 145 146Lstart: 147 .word start 148 149#define MMU_INIT(va,pa,n_sec,attr) \ 150 .word n_sec ; \ 151 .word 4*((va)>>L1_S_SHIFT) ; \ 152 .word (pa)|(attr) ; 153 154mmu_init_table: 155 /* fill all table VA==PA */ 156 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 157 /* map SDRAM VA==PA, WT cacheable */ 158 MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 159 /* map VA 0xc0000000..0xc3ffffff to PA 0x08000000..0x0bffffff */ 160 MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 161 162 /* Map all built-in peripheral registers at 0xfd000000 */ 163 MMU_INIT(SMDK2800_IO_AREA_VBASE, S3C2800_PERIPHERALS, 2, L1_TYPE_S|L1_S_AP(AP_KRW)) 164 .word 0 /* end of table */ 165 166