1/* $NetBSD: smdk2410_start.S,v 1.5 2005/12/11 12:17:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35#include <machine/asm.h> 36#include <arm/armreg.h> 37#include <arm/arm32/pte.h> 38#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 39 40#include <arm/s3c2xx0/s3c2410reg.h> /* for S3C2410_SDRAM_START */ 41#include "opt_smdk2xx0.h" /* SMDK2XX0_CLOCK_CONFIG */ 42 43/* 44 * Kernel start routine for Samsung SMDK2410. 45 * This code is excuted at the very first after the kernel is loaded 46 * by boot program. 47 */ 48 .text 49 50#ifndef SDRAM_START 51#define SDRAM_START S3C2410_SDRAM_START 52#endif 53#define KERNEL_TEXT_ADDR (SDRAM_START+0x00200000) 54 55 .global _C_LABEL(smdk2410_start) 56_C_LABEL(smdk2410_start): 57 /* Disable interrupt */ 58 mrs r0, cpsr 59 orr r0, r0, #I32_bit 60 msr cpsr, r0 61 62#ifdef SMDK2XX0_CLOCK_CONFIG 63 adr r4, clock_config_data 64 65 mov r2, #S3C2410_CLKMAN_BASE 66 ldr r1, [r2, #CLKMAN_CLKSLOW] 67 orr r0, r1, #CLKSLOW_SLOW 68 str r0, [r2, #CLKMAN_CLKSLOW] 69 nop 70 nop 71 72 ldmia r4, {r0,r3} 73 str r0, [r2, #CLKMAN_CLKDIVN] 74 75 str r3, [r2, #CLKMAN_MPLLCON] 76 nop 77 nop 78 79 str r1, [r2, #CLKMAN_CLKSLOW] 80#endif 81 82 /* Are we running on right place ? */ 83 adr r0, _C_LABEL(smdk2410_start) 84 ldr r2, =KERNEL_TEXT_ADDR 85 cmp r0, r2 86 beq smdk2410_start_ram 87 88 /* 89 * move me to RAM 90 */ 91 ldr r1, Lcopy_size 92 adr r0, _C_LABEL(smdk2410_start) 93 add r1, r1, #3 94 mov r1, r1, LSR #2 95 mov r4, r2 96 97 cmp r0, r2 98 bhs 5f 99 100 /* src < dest. copy from top */ 101 add r0,r0,r1,LSL #2 102 add r2,r2,r1,LSL #2 103 1043: ldr r3,[r0,#-4]! 105 str r3,[r2,#-4]! 106 subs r1,r1,#1 107 bhi 3b 108 b 7f 109 110 /* src >= dest. copy from bottom */ 1115: ldr r3,[r0],#4 112 str r3,[r2],#4 113 subs r1,r1,#1 114 bhi 5b 115 1167: 117 /* Jump to RAM */ 118 ldr r0, Lstart_off 119 add pc, r4, r0 120 121Lcopy_size: .word _edata-_C_LABEL(smdk2410_start) 122Lstart_off: .word smdk2410_start_ram-_C_LABEL(smdk2410_start) 123 124smdk2410_start_ram: 125 /* 126 * Kernel is loaded in SDRAM (0x30200000..), and is expected to run 127 * in VA 0xc0200000.. 128 */ 129 130 /* Disable MMU for a while */ 131 mrc p15, 0, r2, c1, c0, 0 132 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 133 mcr p15, 0, r2, c1, c0, 0 134 135 nop 136 nop 137 nop 138 139 mov r0,#SDRAM_START /* pagetable */ 140 adr r4, mmu_init_table 141 b 2f 1421: 143 str r3, [r0, r2] 144 add r2, r2, #4 145 add r3, r3, #(L1_S_SIZE) 146 adds r1, r1, #-1 147 bhi 1b 1482: 149 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 150 cmp r1, #0 151 bne 1b 152 153 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 154 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 155 156 /* Set the Domain Access register. Very important! */ 157 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 158 mcr p15, 0, r0, c3, c0, 0 159 160 /* Enable MMU */ 161 mrc p15, 0, r0, c1, c0, 0 162 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 163 mcr p15, 0, r0, c1, c0, 0 164 165 nop 166 nop 167 nop 168 169 /* Jump to kernel code in TRUE VA */ 170 adr r0, Lstart 171 ldr pc, [r0] 172 173Lstart: 174 .word start 175 176 .macro clock_data hdivn, pdivn, mdiv, pdiv, sdiv 177 .word (\hdivn)<<1 | \pdivn 178 .word (\mdiv)<<PLLCON_MDIV_SHIFT | (\pdiv)<<PLLCON_PDIV_SHIFT | (\sdiv)<<PLLCON_SDIV_SHIFT 179 .endm 180#ifdef SMDK2XX0_CLOCK_CONFIG 181clock_config_data: 182 clock_data SMDK2XX0_CLOCK_CONFIG 183#endif 184 185#define MMU_INIT(va,pa,n_sec,attr) \ 186 .word n_sec ; \ 187 .word 4*((va)>>L1_S_SHIFT) ; \ 188 .word (pa)|(attr) ; 189 190mmu_init_table: 191 /* fill all table VA==PA */ 192 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 193 /* map SDRAM VA==PA, WT cacheable */ 194 MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 195 /* map VA 0xc0000000..0xc3ffffff to PA 0x30000000..0x33ffffff */ 196 MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 197 198 .word 0 /* end of table */ 199 200