1 /* $NetBSD: marvell_machdep.c,v 1.5 2011/06/30 20:09:25 wiz Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.5 2011/06/30 20:09:25 wiz Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mvsocgppvar.h> 69 70 #include <evbarm/marvell/marvellreg.h> 71 #include <evbarm/marvell/marvellvar.h> 72 73 #include <ddb/db_extern.h> 74 #include <ddb/db_sym.h> 75 76 #include "ksyms.h" 77 78 79 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 80 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 81 #define KERNEL_VM_BASE (KERNEL_BASE + 0x01000000) 82 83 /* 84 * The range 0xc1000000 - 0xccffffff is available for kernel VM space 85 * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff 86 */ 87 #define KERNEL_VM_SIZE 0x0c000000 88 89 /* 90 * Address to call from cpu_reset() to reset the machine. 91 * This is machine architecture dependent as it varies depending 92 * on where the ROM appears when you turn the MMU off. 93 */ 94 95 u_int cpu_reset_address = 0xffff0000; 96 97 /* Define various stack sizes in pages */ 98 #define IRQ_STACK_SIZE 1 99 #define ABT_STACK_SIZE 1 100 #ifdef IPKDB 101 #define UND_STACK_SIZE 2 102 #else 103 #define UND_STACK_SIZE 1 104 #endif 105 106 BootConfig bootconfig; /* Boot config storage */ 107 static char bootargs[MAX_BOOT_STRING]; 108 char *boot_args = NULL; 109 110 vm_offset_t physical_start; 111 vm_offset_t physical_freestart; 112 vm_offset_t physical_freeend; 113 vm_offset_t physical_end; 114 u_int free_pages; 115 int physmem = 0; 116 117 /* Physical and virtual addresses for some global pages */ 118 pv_addr_t systempage; 119 pv_addr_t irqstack; 120 pv_addr_t undstack; 121 pv_addr_t abtstack; 122 pv_addr_t kernelstack; 123 124 vm_offset_t msgbufphys; 125 126 extern u_int data_abort_handler_address; 127 extern u_int prefetch_abort_handler_address; 128 extern u_int undefined_handler_address; 129 130 extern char _end[]; 131 132 #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 133 #define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */ 134 #define KERNEL_PT_KERNEL_NUM 4 135 #define KERNEL_PT_VMDATA (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM) 136 /* Page tables for mapping kernel VM */ 137 #define KERNEL_PT_VMDATA_NUM 4 /* start with 16MB of KVM */ 138 #define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM) 139 140 pv_addr_t kernel_pt_table[NUM_KERNEL_PTS]; 141 142 /* 143 * Macros to translate between physical and virtual for a subset of the 144 * kernel address space. *Not* for general use. 145 */ 146 #define KERNEL_BASE_PHYS physical_start 147 #define KERN_VTOPHYS(va) \ 148 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 149 #define KERN_PHYSTOV(pa) \ 150 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 151 152 153 #include "com.h" 154 #if NCOM > 0 155 #include <dev/ic/comreg.h> 156 #include <dev/ic/comvar.h> 157 #endif 158 159 #ifndef CONSPEED 160 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 161 #endif 162 #ifndef CONMODE 163 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 164 165 int comcnspeed = CONSPEED; 166 int comcnmode = CONMODE; 167 #endif 168 169 #include "opt_kgdb.h" 170 #ifdef KGDB 171 #include <sys/kgdb.h> 172 #endif 173 174 static void marvell_device_register(device_t, void *); 175 #if NGTPCI > 0 || NMVPEX > 0 176 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 177 #endif 178 179 static void 180 marvell_system_reset(void) 181 { 182 /* unmask soft reset */ 183 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 184 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 185 /* assert soft reset */ 186 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 187 /* if we're still running, jump to the reset address */ 188 cpu_reset(); 189 /*NOTREACHED*/ 190 } 191 192 void 193 cpu_reboot(int howto, char *bootstr) 194 { 195 196 /* 197 * If we are still cold then hit the air brakes 198 * and crash to earth fast 199 */ 200 if (cold) { 201 doshutdownhooks(); 202 printf("The operating system has halted.\r\n"); 203 printf("Please press any key to reboot.\r\n"); 204 cngetc(); 205 printf("rebooting...\r\n"); 206 marvell_system_reset(); 207 } 208 209 /* 210 * If RB_NOSYNC was not specified sync the discs. 211 * Note: Unless cold is set to 1 here, syslogd will die during the 212 * unmount. It looks like syslogd is getting woken up only to find 213 * that it cannot page part of the binary in as the filesystem has 214 * been unmounted. 215 */ 216 if (!(howto & RB_NOSYNC)) 217 bootsync(); 218 219 /* Say NO to interrupts */ 220 splhigh(); 221 222 /* Do a dump if requested. */ 223 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 224 dumpsys(); 225 226 /* Run any shutdown hooks */ 227 doshutdownhooks(); 228 229 /* Make sure IRQ's are disabled */ 230 IRQdisable; 231 232 if (howto & RB_HALT) { 233 printf("The operating system has halted.\r\n"); 234 printf("Please press any key to reboot.\r\n"); 235 cngetc(); 236 } 237 238 printf("rebooting...\r\n"); 239 marvell_system_reset(); 240 241 /*NOTREACHED*/ 242 } 243 244 static inline 245 pd_entry_t * 246 read_ttb(void) 247 { 248 long ttb; 249 250 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 251 252 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 253 } 254 255 /* 256 * Static device mappings. These peripheral registers are mapped at 257 * fixed virtual addresses very early in initarm() so that we can use 258 * them while booting the kernel, and stay at the same address 259 * throughout whole kernel's life time. 260 * 261 * We use this table twice; once with bootstrap page table, and once 262 * with kernel's page table which we build up in initarm(). 263 * 264 * Since we map these registers into the bootstrap page table using 265 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 266 * registers segment-aligned and segment-rounded in order to avoid 267 * using the 2nd page tables. 268 */ 269 #define _A(a) ((a) & ~L1_S_OFFSET) 270 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 271 272 static const struct pmap_devmap marvell_devmap[] = { 273 { 274 MARVELL_INTERREGS_VBASE, 275 _A(MARVELL_INTERREGS_PBASE), 276 _S(MARVELL_INTERREGS_SIZE), 277 VM_PROT_READ|VM_PROT_WRITE, 278 PTE_NOCACHE, 279 }, 280 281 { 0, 0, 0, 0, 0 } 282 }; 283 284 #undef _A 285 #undef _S 286 287 extern uint32_t *u_boot_args[]; 288 289 /* 290 * u_int initarm(...) 291 * 292 * Initial entry point on startup. This gets called before main() is 293 * entered. 294 * It should be responsible for setting up everything that must be 295 * in place when main is called. 296 * This includes 297 * Taking a copy of the boot configuration structure. 298 * Initialising the physical console so characters can be printed. 299 * Setting up page tables for the kernel 300 * Relocating the kernel to the bottom of physical memory 301 */ 302 u_int 303 initarm(void *arg) 304 { 305 uint32_t target, attr, base, size; 306 u_int l1pagetable; 307 int loop, pt_index, cs, memtag = 0, iotag = 0, window; 308 309 /* map some peripheral registers */ 310 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 311 312 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 313 314 /* Get ready for splfoo() */ 315 switch (mvsoc_model()) { 316 #ifdef ORION 317 case MARVELL_ORION_1_88F1181: 318 case MARVELL_ORION_1_88F5082: 319 case MARVELL_ORION_1_88F5180N: 320 case MARVELL_ORION_1_88F5181: 321 case MARVELL_ORION_1_88F5182: 322 case MARVELL_ORION_1_88F6082: 323 case MARVELL_ORION_1_88F6183: 324 case MARVELL_ORION_1_88W8660: 325 case MARVELL_ORION_2_88F1281: 326 case MARVELL_ORION_2_88F5281: 327 orion_intr_bootstrap(); 328 329 memtag = ORION_TAG_PEX0_MEM; 330 iotag = ORION_TAG_PEX0_IO; 331 nwindow = ORION_MLMB_NWINDOW; 332 nremap = ORION_MLMB_NREMAP; 333 334 orion_getclks(MARVELL_INTERREGS_VBASE); 335 if (mvTclk == 166666667) /* 166MHz */ 336 mvTclk = 166664740; /* ???? */ 337 break; 338 #endif /* ORION */ 339 340 #ifdef KIRKWOOD 341 case MARVELL_KIRKWOOD_88F6180: 342 case MARVELL_KIRKWOOD_88F6192: 343 case MARVELL_KIRKWOOD_88F6281: 344 kirkwood_intr_bootstrap(); 345 346 memtag = KIRKWOOD_TAG_PEX_MEM; 347 iotag = KIRKWOOD_TAG_PEX_IO; 348 nwindow = KIRKWOOD_MLMB_NWINDOW; 349 nremap = KIRKWOOD_MLMB_NREMAP; 350 351 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 352 break; 353 #endif /* KIRKWOOD */ 354 355 #ifdef MV78XX0 356 case MARVELL_MV78XX0_MV78100: 357 case MARVELL_MV78XX0_MV78200: 358 mv78xx0_intr_bootstrap(); 359 360 memtag = MV78XX0_TAG_PEX_MEM; 361 iotag = MV78XX0_TAG_PEX_IO; 362 nwindow = MV78XX0_MLMB_NWINDOW; 363 nremap = MV78XX0_MLMB_NREMAP; 364 365 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 366 break; 367 #endif /* MV78XX0 */ 368 369 default: 370 /* We can't output console here yet... */ 371 panic("unknown model...\n"); 372 373 /* NOTREACHED */ 374 } 375 376 /* Reset PCI-Express space to window register. */ 377 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 378 write_mlmbreg(MVSOC_MLMB_WCR(window), 379 MVSOC_MLMB_WCR_WINEN | 380 MVSOC_MLMB_WCR_TARGET(target) | 381 MVSOC_MLMB_WCR_ATTR(attr) | 382 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 383 write_mlmbreg(MVSOC_MLMB_WBR(window), 384 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 385 #ifdef PCI_NETBSD_CONFIGURE 386 if (window < nremap) { 387 write_mlmbreg(MVSOC_MLMB_WRLR(window), 388 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 389 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 390 } 391 #endif 392 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 393 write_mlmbreg(MVSOC_MLMB_WCR(window), 394 MVSOC_MLMB_WCR_WINEN | 395 MVSOC_MLMB_WCR_TARGET(target) | 396 MVSOC_MLMB_WCR_ATTR(attr) | 397 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 398 write_mlmbreg(MVSOC_MLMB_WBR(window), 399 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 400 #ifdef PCI_NETBSD_CONFIGURE 401 if (window < nremap) { 402 write_mlmbreg(MVSOC_MLMB_WRLR(window), 403 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 404 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 405 } 406 #endif 407 408 /* 409 * Heads up ... Setup the CPU / MMU / TLB functions 410 */ 411 if (set_cpufuncs()) 412 panic("cpu not recognized!"); 413 414 /* 415 * U-Boot doesn't use the virtual memory. 416 * 417 * Physical Address Range Description 418 * ----------------------- ---------------------------------- 419 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 420 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 421 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 422 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 423 * 0xf1000000 - 0xf10fffff SoC Internal Registers 424 */ 425 426 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 427 428 consinit(); 429 430 /* Talk to the user */ 431 #define BDSTR(s) _BDSTR(s) 432 #define _BDSTR(s) #s 433 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 434 435 /* copy command line U-Boot gave us */ 436 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 437 438 #ifdef VERBOSE_INIT_ARM 439 printf("initarm: Configuring system ...\n"); 440 #endif 441 442 bootconfig.dramblocks = 0; 443 physical_end = physmem = 0; 444 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 445 mvsoc_target(cs, &target, &attr, &base, &size); 446 if (size == 0) 447 continue; 448 449 bootconfig.dram[bootconfig.dramblocks].address = base; 450 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 451 452 if (base != physical_end) 453 panic("memory hole not support"); 454 455 physical_end += size; 456 physmem += size / PAGE_SIZE; 457 458 bootconfig.dramblocks++; 459 } 460 461 /* 462 * Set up the variables that define the availablilty of 463 * physical memory. For now, we're going to set 464 * physical_freestart to 0xa0008000 (where the kernel 465 * was loaded), and allocate the memory we need downwards. 466 * If we get too close to the L1 table that we set up, we 467 * will panic. We will update physical_freestart and 468 * physical_freeend later to reflect what pmap_bootstrap() 469 * wants to see. 470 * 471 * XXX pmap_bootstrap() needs an enema. 472 */ 473 physical_start = bootconfig.dram[0].address; 474 475 /* 476 * Our kernel is at the beginning of memory, so set our free space to 477 * all the memory after the kernel. 478 */ 479 physical_freestart = KERN_VTOPHYS(round_page((vaddr_t)_end)); 480 physical_freeend = physical_end; 481 482 #ifdef VERBOSE_INIT_ARM 483 /* Tell the user about the memory */ 484 printf("physmemory: %d pages at 0x%08lx -> 0x%08lx\n", physmem, 485 physical_start, physical_end - 1); 486 #endif 487 488 /* 489 * Okay, the kernel starts 8kB in from the bottom of physical 490 * memory. We are going to allocate our bootstrap pages upwards 491 * from physical_freestart. 492 * 493 * We need to allocate some fixed page tables to get the kernel 494 * going. We allocate one page directory and a number of page 495 * tables and store the physical addresses in the kernel_pt_table 496 * array. 497 * 498 * The kernel page directory must be on a 16K boundary. The page 499 * tables must be on 4K bounaries. What we do is allocate the 500 * page directory on the first 16K boundary that we encounter, and 501 * the page tables on 4K boundaries otherwise. Since we allocate 502 * at least 3 L2 page tables, we are guaranteed to encounter at 503 * least one 16K aligned region. 504 */ 505 506 #ifdef VERBOSE_INIT_ARM 507 printf("Allocating page tables\n"); 508 #endif 509 510 free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE; 511 512 #ifdef VERBOSE_INIT_ARM 513 printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n", 514 physical_freestart, free_pages, free_pages); 515 #endif 516 517 /* 518 * Define a macro to simplify memory allocation. As we allocate the 519 * memory, make sure that we don't walk over our temporary first level 520 * translation table. 521 */ 522 #define valloc_pages(var, np) \ 523 (var).pv_pa = physical_freestart; \ 524 physical_freestart += ((np) * PAGE_SIZE); \ 525 if (physical_freestart > (physical_freeend - L1_TABLE_SIZE)) \ 526 panic("initarm: out of memory"); \ 527 free_pages -= (np); \ 528 (var).pv_va = KERN_PHYSTOV((var).pv_pa); \ 529 memset((char *)(var).pv_va, 0, ((np) * PAGE_SIZE)); 530 531 pt_index = 0; 532 kernel_l1pt.pv_pa = 0; 533 kernel_l1pt.pv_va = 0; 534 for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) { 535 /* Are we 16KB aligned for an L1 ? */ 536 if ((physical_freestart & (L1_TABLE_SIZE - 1)) == 0 && 537 kernel_l1pt.pv_pa == 0) { 538 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 539 } else { 540 valloc_pages(kernel_pt_table[pt_index], 541 L2_TABLE_SIZE / PAGE_SIZE); 542 ++pt_index; 543 } 544 } 545 546 /* This should never be able to happen but better confirm that. */ 547 if (!kernel_l1pt.pv_pa || 548 (kernel_l1pt.pv_pa & (L1_TABLE_SIZE - 1)) != 0) 549 panic("initarm: Failed to align the kernel page directory"); 550 551 /* 552 * Allocate a page for the system page mapped to V0x00000000 553 * This page will just contain the system vectors and can be 554 * shared by all processes. 555 */ 556 valloc_pages(systempage, 1); 557 systempage.pv_va = 0x00000000; 558 559 /* Allocate stacks for all modes */ 560 valloc_pages(irqstack, IRQ_STACK_SIZE); 561 valloc_pages(abtstack, ABT_STACK_SIZE); 562 valloc_pages(undstack, UND_STACK_SIZE); 563 valloc_pages(kernelstack, UPAGES); 564 565 #ifdef VERBOSE_INIT_ARM 566 printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, 567 irqstack.pv_va); 568 printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, 569 abtstack.pv_va); 570 printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, 571 undstack.pv_va); 572 printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, 573 kernelstack.pv_va); 574 #endif 575 576 /* Allocate the message buffer. */ 577 { 578 pv_addr_t msgbuf; 579 580 valloc_pages(msgbuf, round_page(MSGBUFSIZE) / PAGE_SIZE); 581 msgbufphys = msgbuf.pv_pa; 582 } 583 584 /* 585 * Ok we have allocated physical pages for the primary kernel 586 * page tables 587 */ 588 589 #ifdef VERBOSE_INIT_ARM 590 printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa); 591 #endif 592 593 /* 594 * Now we start construction of the L1 page table 595 * We start by mapping the L2 page tables into the L1. 596 * This means that we can replace L1 mappings later on if necessary 597 */ 598 l1pagetable = kernel_l1pt.pv_va; 599 600 /* Map the L2 pages tables in the L1 page table */ 601 pmap_link_l2pt(l1pagetable, 0x00000000, 602 &kernel_pt_table[KERNEL_PT_SYS]); 603 for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) 604 pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000, 605 &kernel_pt_table[KERNEL_PT_KERNEL + loop]); 606 for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++) 607 pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000, 608 &kernel_pt_table[KERNEL_PT_VMDATA + loop]); 609 610 /* update the top of the kernel VM */ 611 pmap_curmaxkvaddr = 612 KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000); 613 614 #ifdef VERBOSE_INIT_ARM 615 printf("Mapping kernel\n"); 616 #endif 617 618 /* Now we fill in the L2 pagetable for the kernel static code/data */ 619 { 620 extern char etext[], _end[]; 621 size_t textsize = (uintptr_t)etext - KERNEL_TEXT_BASE; 622 size_t totalsize = (uintptr_t)_end - KERNEL_TEXT_BASE; 623 u_int logical; 624 625 textsize = (textsize + PGOFSET) & ~PGOFSET; 626 totalsize = (totalsize + PGOFSET) & ~PGOFSET; 627 628 logical = 0x00000000; /* offset of kernel in RAM */ 629 630 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 631 physical_start + logical, textsize, 632 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 633 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 634 physical_start + logical, totalsize - textsize, 635 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 636 } 637 638 #ifdef VERBOSE_INIT_ARM 639 printf("Constructing L2 page tables\n"); 640 #endif 641 642 /* Map the stack pages */ 643 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 644 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 645 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 646 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 647 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 648 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 649 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 650 UPAGES * PAGE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_CACHE); 651 652 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 653 L1_TABLE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_PAGETABLE); 654 655 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) 656 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, 657 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, 658 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 659 660 /* Map the vector page. */ 661 pmap_map_entry(l1pagetable, ARM_VECTORS_LOW, systempage.pv_pa, 662 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 663 664 /* 665 * Map integrated peripherals at same address in first level page 666 * table so that we can continue to use console. 667 */ 668 pmap_devmap_bootstrap(l1pagetable, marvell_devmap); 669 670 /* 671 * Now we have the real page tables in place so we can switch to them. 672 * Once this is done we will be running with the REAL kernel page 673 * tables. 674 */ 675 676 /* Switch tables */ 677 #ifdef VERBOSE_INIT_ARM 678 printf("switching to new L1 page table @%#lx...", kernel_l1pt.pv_pa); 679 #endif 680 681 cpu_setttb(kernel_l1pt.pv_pa); 682 cpu_tlb_flushID(); 683 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 684 685 /* 686 * Moved from cpu_startup() as data_abort_handler() references 687 * this during uvm init. 688 */ 689 uvm_lwp_setuarea(&lwp0, kernelstack.pv_va); 690 691 #ifdef VERBOSE_INIT_ARM 692 printf("bootstrap done.\n"); 693 #endif 694 695 arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL); 696 697 /* 698 * Pages were allocated during the secondary bootstrap for the 699 * stacks for different CPU modes. 700 * We must now set the r13 registers in the different CPU modes to 701 * point to these stacks. 702 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 703 * of the stack memory. 704 */ 705 #ifdef VERBOSE_INIT_ARM 706 printf("init subsystems: stacks "); 707 #endif 708 709 set_stackptr(PSR_IRQ32_MODE, 710 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 711 set_stackptr(PSR_ABT32_MODE, 712 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 713 set_stackptr(PSR_UND32_MODE, 714 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 715 716 /* 717 * Well we should set a data abort handler. 718 * Once things get going this will change as we will need a proper 719 * handler. 720 * Until then we will use a handler that just panics but tells us 721 * why. 722 * Initialisation of the vectors will just panic on a data abort. 723 * This just fills in a slightly better one. 724 */ 725 #ifdef VERBOSE_INIT_ARM 726 printf("vectors "); 727 #endif 728 data_abort_handler_address = (u_int)data_abort_handler; 729 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 730 undefined_handler_address = (u_int)undefinedinstruction_bounce; 731 732 /* Initialise the undefined instruction handlers */ 733 #ifdef VERBOSE_INIT_ARM 734 printf("undefined "); 735 #endif 736 undefined_init(); 737 738 /* Load memory into UVM. */ 739 #ifdef VERBOSE_INIT_ARM 740 printf("page "); 741 #endif 742 uvm_setpagesize(); /* initialize PAGE_SIZE-dependent variables */ 743 uvm_page_physload(atop(physical_freestart), atop(physical_freeend), 744 atop(physical_freestart), atop(physical_freeend), 745 VM_FREELIST_DEFAULT); 746 747 /* Boot strap pmap telling it where the kernel page table is */ 748 #ifdef VERBOSE_INIT_ARM 749 printf("pmap "); 750 #endif 751 pmap_bootstrap(KERNEL_VM_BASE, KERNEL_VM_BASE + KERNEL_VM_SIZE); 752 753 #ifdef VERBOSE_INIT_ARM 754 printf("done.\n"); 755 #endif 756 757 #ifdef __HAVE_MEMORY_DISK__ 758 md_root_setconf(memory_disk, sizeof memory_disk); 759 #endif 760 761 boot_args = bootargs; 762 parse_mi_bootargs(boot_args); 763 764 #ifdef BOOTHOWTO 765 boothowto |= BOOTHOWTO; 766 #endif 767 768 #ifdef KGDB 769 if (boothowto & RB_KDB) { 770 kgdb_debug_init = 1; 771 kgdb_connect(1); 772 } 773 #endif 774 775 #ifdef DDB 776 db_machine_init(); 777 if (boothowto & RB_KDB) 778 Debugger(); 779 #endif 780 781 /* we've a specific device_register routine */ 782 evbarm_device_register = marvell_device_register; 783 784 /* We return the new stack pointer address */ 785 return(kernelstack.pv_va + USPACE_SVC_STACK_TOP); 786 } 787 788 void 789 consinit(void) 790 { 791 static int consinit_called = 0; 792 793 if (consinit_called != 0) 794 return; 795 796 consinit_called = 1; 797 798 #if NCOM > 0 799 { 800 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 801 uint32_t, int); 802 803 if (mvuart_cnattach(&mvsoc_bs_tag, 804 MARVELL_INTERREGS_VBASE + MVSOC_COM0_BASE, 805 comcnspeed, mvTclk, comcnmode)) 806 panic("can't init serial console"); 807 } 808 #else 809 panic("serial console not configured"); 810 #endif 811 } 812 813 814 static void 815 marvell_device_register(device_t dev, void *aux) 816 { 817 prop_dictionary_t dict = device_properties(dev); 818 819 #if NCOM > 0 820 if (device_is_a(dev, "com") && 821 device_is_a(device_parent(dev), "mvsoc")) 822 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 823 #endif 824 if (device_is_a(dev, "gtidmac")) { 825 prop_dictionary_set_uint32(dict, 826 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 827 prop_dictionary_set_uint32(dict, 828 "xore-irq-begin", ORION_IRQ_XOR0); 829 } 830 #if NGTPCI > 0 && defined(ORION) 831 if (device_is_a(dev, "gtpci")) { 832 extern struct bus_space 833 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 834 extern struct arm32_pci_chipset arm32_gtpci_chipset; 835 836 prop_data_t io_bs_tag, mem_bs_tag, pc; 837 prop_array_t int2gpp; 838 prop_number_t gpp; 839 uint64_t start, end; 840 int i, j; 841 static struct { 842 const char *boardtype; 843 int pin[PCI_INTERRUPT_PIN_MAX]; 844 } hints[] = { 845 { "kuronas_x4", 846 { 11, PCI_INTERRUPT_PIN_NONE } }, 847 848 { NULL, 849 { PCI_INTERRUPT_PIN_NONE } }, 850 }; 851 852 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 853 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 854 855 io_bs_tag = prop_data_create_data_nocopy( 856 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 857 KASSERT(io_bs_tag != NULL); 858 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 859 prop_object_release(io_bs_tag); 860 mem_bs_tag = prop_data_create_data_nocopy( 861 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 862 KASSERT(mem_bs_tag != NULL); 863 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 864 prop_object_release(mem_bs_tag); 865 866 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 867 sizeof(struct arm32_pci_chipset)); 868 KASSERT(pc != NULL); 869 prop_dictionary_set(dict, "pci-chipset", pc); 870 prop_object_release(pc); 871 872 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 873 prop_dictionary_set_uint64(dict, "iostart", start); 874 prop_dictionary_set_uint64(dict, "ioend", end); 875 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 876 prop_dictionary_set_uint64(dict, "memstart", start); 877 prop_dictionary_set_uint64(dict, "memend", end); 878 prop_dictionary_set_uint32(dict, 879 "cache-line-size", arm_dcache_align); 880 881 /* Setup the hint for interrupt-pin. */ 882 #define BDSTR(s) _BDSTR(s) 883 #define _BDSTR(s) #s 884 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 885 for (i = 0; hints[i].boardtype != NULL; i++) 886 if (THIS_BOARD(hints[i].boardtype)) 887 break; 888 if (hints[i].boardtype == NULL) 889 return; 890 891 int2gpp = 892 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 893 894 /* first set dummy */ 895 gpp = prop_number_create_integer(0); 896 prop_array_add(int2gpp, gpp); 897 prop_object_release(gpp); 898 899 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 900 gpp = prop_number_create_integer(hints[i].pin[j]); 901 prop_array_add(int2gpp, gpp); 902 prop_object_release(gpp); 903 } 904 prop_dictionary_set(dict, "int2gpp", int2gpp); 905 } 906 #endif /* NGTPCI > 0 && defined(ORION) */ 907 #if NMVPEX > 0 908 if (device_is_a(dev, "mvpex")) { 909 #ifdef ORION 910 extern struct bus_space 911 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 912 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 913 #endif 914 #ifdef KIRKWOOD 915 extern struct bus_space 916 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag; 917 #endif 918 extern struct arm32_pci_chipset 919 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 920 921 struct marvell_attach_args *mva = aux; 922 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 923 struct arm32_pci_chipset *arm32_mvpex_chipset; 924 prop_data_t io_bs_tag, mem_bs_tag, pc; 925 uint64_t start, end; 926 int iotag, memtag; 927 928 switch (mvsoc_model()) { 929 #ifdef ORION 930 case MARVELL_ORION_1_88F5180N: 931 case MARVELL_ORION_1_88F5181: 932 case MARVELL_ORION_1_88F5182: 933 case MARVELL_ORION_1_88W8660: 934 case MARVELL_ORION_2_88F5281: 935 if (mva->mva_offset == MVSOC_PEX_BASE) { 936 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 937 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 938 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 939 iotag = ORION_TAG_PEX0_IO; 940 memtag = ORION_TAG_PEX0_MEM; 941 } else { 942 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 943 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 944 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 945 iotag = ORION_TAG_PEX1_IO; 946 memtag = ORION_TAG_PEX1_MEM; 947 } 948 break; 949 #endif 950 951 #ifdef KIRKWOOD 952 case MARVELL_KIRKWOOD_88F6180: 953 case MARVELL_KIRKWOOD_88F6192: 954 case MARVELL_KIRKWOOD_88F6281: 955 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 956 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 957 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 958 iotag = KIRKWOOD_TAG_PEX_IO; 959 memtag = KIRKWOOD_TAG_PEX_MEM; 960 break; 961 #endif 962 963 default: 964 return; 965 } 966 967 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 968 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 969 970 io_bs_tag = prop_data_create_data_nocopy( 971 mvpex_io_bs_tag, sizeof(struct bus_space)); 972 KASSERT(io_bs_tag != NULL); 973 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 974 prop_object_release(io_bs_tag); 975 mem_bs_tag = prop_data_create_data_nocopy( 976 mvpex_mem_bs_tag, sizeof(struct bus_space)); 977 KASSERT(mem_bs_tag != NULL); 978 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 979 prop_object_release(mem_bs_tag); 980 981 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 982 sizeof(struct arm32_pci_chipset)); 983 KASSERT(pc != NULL); 984 prop_dictionary_set(dict, "pci-chipset", pc); 985 prop_object_release(pc); 986 987 marvell_startend_by_tag(iotag, &start, &end); 988 prop_dictionary_set_uint64(dict, "iostart", start); 989 prop_dictionary_set_uint64(dict, "ioend", end); 990 marvell_startend_by_tag(memtag, &start, &end); 991 prop_dictionary_set_uint64(dict, "memstart", start); 992 prop_dictionary_set_uint64(dict, "memend", end); 993 prop_dictionary_set_uint32(dict, 994 "cache-line-size", arm_dcache_align); 995 } 996 #endif 997 } 998 999 #if NGTPCI > 0 || NMVPEX > 0 1000 static void 1001 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 1002 { 1003 uint32_t base, size; 1004 int win; 1005 1006 win = mvsoc_target(tag, NULL, NULL, &base, &size); 1007 if (size != 0) { 1008 if (win < nremap) 1009 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 1010 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 1011 else 1012 *start = base; 1013 *end = *start + size - 1; 1014 } 1015 } 1016 #endif 1017