1/* $NetBSD: ixm1200_start.S,v 1.3 2008/04/28 20:23:17 martin Exp $ */ 2 3/* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA and Naoto Shimazaki. 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Jason R. Thorpe. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include "assym.h" 36 37#include <arm/asm.h> 38#include <arm/armreg.h> 39#include <arm/arm32/pte.h> 40 41 .section .start,"ax",%progbits 42 43 .global _C_LABEL(ixm1200_start) 44_C_LABEL(ixm1200_start): 45 /* 46 * Disable IRQ and FIQ 47 */ 48 mrs r3, cpsr_all 49 orr r1, r3, #(I32_bit | F32_bit) 50 msr cpsr_all, r1 51 52 /* 53 * Setup coprocessor 15. 54 * 55 * We assume we've been loaded VA == PA, or that the MMU is 56 * disabled. We will go ahead and disable the MMU here 57 * so that we don't have to worry about flushing caches, etc. 58 */ 59 60 /* CONTROL_CP15 */ 61 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */ 62 bic r0, r0, #CPU_CONTROL_MMU_ENABLE 63 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE 64 orr r0, r0, #CPU_CONTROL_DC_ENABLE 65 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE 66 bic r0, r0, #CPU_CONTROL_BEND_ENABLE 67 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 68 bic r0, r0, #CPU_CONTROL_ROM_ENABLE 69 orr r0, r0, #CPU_CONTROL_IC_ENABLE 70 bic r0, r0, #CPU_CONTROL_VECRELOC 71 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */ 72 73 nop 74 nop 75 nop 76 77 /* TRANSLATION_TABLE_BASE */ 78 mov r0, #0 79 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 80 81 /* DOMAIN_ACCESS_CONTROL */ 82 mov r0, #0x00000001 /* use domain 0 as client */ 83 mcr p15, 0, r0, c3, c0 ,0 /* write domain */ 84 85 /* CACHE_CONTROL_OPERATIONS */ 86 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */ 87 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */ 88 89 /* TLB_OPERATIONS */ 90 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 91 92 /* READ_BUFFER_OPERATIONS */ 93 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */ 94 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */ 95 96 /* PROCESS_ID_VIRTUAL_ADDR_MAPPING */ 97 mov r0, #0 98 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0 99 100 /* BREAKPOINT_DEBUG_SUPPORT */ 101 mov r0, #0 102 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */ 103 mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 */ 104 mcr p15, 0, r0, c15, c2 ,0 /* DBMR = 0 */ 105 mcr p15, 0, r0, c15, c3 ,0 /* DBCR = 0 (never watch) */ 106 mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */ 107 108 /* 109 * We want to construct a memory map that maps us 110 * VA == PA (SDRAM at 0xc0000000). We create these mappings 111 * uncached and unbuffered to be safe. 112 * 113 * We also want to map the various devices we want to 114 * talk to VA == PA during bootstrap. 115 * 116 * We also want to map the v0xf0000000 == p0x90000000 117 * to output eary bootstrup messages to the console. 118 * 119 * We just use section mappings for all of this to make it easy. 120 * 121 * We will put the L1 table to do all this at c01fc000 122 * where is our KERNEL_TEXT_BASE - sizeof(L1 table). 123 */ 124 125 /* 126 * Step 1: Map the entire address space VA == PA. 127 */ 128 ldr r0, Ltable 129 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 130 mov r2, #(L1_S_SIZE) /* 1MB / section */ 131 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 132 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 1331: 134 str r3, [r0], #4 135 add r3, r3, r2 136 subs r1, r1, #1 137 bgt 1b 138 139 /* 140 * Step 2: Map VA 0xf0000000->0xf0100000 to PA 0x90000000->0x90100000. 141 */ 142 ldr r0, Ltable 143 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 144 mov r3, #0x90000000 145 add r3, r3, #0x00100000 /* set 0x90100000 to r3 */ 146 orr r3, r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 147 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 148 str r3, [r0] 149 150 /* OK! Page table is set up. Give it to the CPU. */ 151 ldr r0, Ltable 152 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 153 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 154 155 /* Get ready to jump to the "real" kernel entry point... */ 156 ldr r0, Lstart 157 158 /* OK, let's enable the MMU. */ 159 mrc p15, 0, r1, c1, c0 ,0 /* read ctrl */ 160 orr r1, r1, #CPU_CONTROL_MMU_ENABLE 161 mcr p15, 0, r1, c1, c0 ,0 /* write ctrl */ 162 163 nop 164 nop 165 nop 166 167 /* CPWAIT sequence to make sure the MMU is on... */ 168 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 169 mov r2, r2 /* force it to complete */ 170 mov pc, r0 /* leap to kernel entry point! */ 171 172Lstart: 173 .word start 174 175Ltable: 176 .word 0xc0200000 - 0x4000 /* our KERNEL_TEXT_BASE - 16KB */ 177 178/* end of ixm1200_start.S */ 179