1 /* $NetBSD: iq80310_intr.h,v 1.7 2008/04/27 18:58:46 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IQ80310_INTR_H_ 39 #define _IQ80310_INTR_H_ 40 41 #include "opt_iop310.h" 42 43 #include <arm/armreg.h> 44 #include <arm/cpufunc.h> 45 46 #include <arm/xscale/i80200reg.h> 47 #include <arm/xscale/i80200var.h> 48 49 #if defined(IOP310_TEAMASA_NPWR) 50 /* 51 * We have 5 interrupt source bits -- all in XINT3. All interrupts 52 * can be masked in the CPLD. 53 */ 54 #define IRQ_BITS 0x1f 55 #define IRQ_BITS_ALWAYS_ON 0x00 56 #else /* Default to stock IQ80310 */ 57 /* 58 * We have 8 interrupt source bits -- 5 in the XINT3 register, and 3 59 * in the XINT0 register (the upper 3). Note that the XINT0 IRQs 60 * (SPCI INTA, INTB, and INTC) are always enabled, since they can not 61 * be masked out in the CPLD (it provides only status, not masking, 62 * for those interrupts). 63 */ 64 #define IRQ_BITS 0xff 65 #define IRQ_BITS_ALWAYS_ON 0xe0 66 #define IRQ_READ_XINT0 1 /* XXX only if board rev >= F */ 67 #endif /* list of IQ80310-based designs */ 68 69 #ifdef __HAVE_FAST_SOFTINTS 70 void iq80310_do_soft(void); 71 #endif 72 73 static inline int __attribute__((__unused__)) 74 iq80310_splraise(int ipl) 75 { 76 extern int iq80310_imask[]; 77 int old; 78 79 old = curcpl(); 80 set_curcpl(old | iq80310_imask[ipl]); 81 82 /* Don't let the compiler re-order this code with subsequent code */ 83 __insn_barrier(); 84 85 return (old); 86 } 87 88 static inline void __attribute__((__unused__)) 89 iq80310_splx(int new) 90 { 91 extern volatile int iq80310_ipending; 92 int old; 93 94 /* Don't let the compiler re-order this code with preceding code */ 95 __insn_barrier(); 96 97 old = curcpl(); 98 set_curcpl(new); 99 100 #ifdef __HAVE_FAST_SOFTINTS 101 /* If there are software interrupts to process, do it. */ 102 if ((iq80310_ipending & ~IRQ_BITS) & ~new) 103 iq80310_do_soft(); 104 #endif 105 106 /* 107 * If there are pending hardware interrupts (i.e. the 108 * external interrupt is disabled in the ICU), and all 109 * hardware interrupts are being unblocked, then re-enable 110 * the external hardware interrupt. 111 * 112 * XXX We have to wait for ALL hardware interrupts to 113 * XXX be unblocked, because we currently lose if we 114 * XXX get nested interrupts, and I don't know why yet. 115 */ 116 if ((new & IRQ_BITS) == 0 && (iq80310_ipending & IRQ_BITS)) 117 i80200_intr_enable(INTCTL_IM | INTCTL_PM); 118 } 119 120 static inline int __attribute__((__unused__)) 121 iq80310_spllower(int ipl) 122 { 123 extern int iq80310_imask[]; 124 const int old = curcpl(); 125 126 iq80310_splx(iq80310_imask[ipl]); 127 return (old); 128 } 129 130 #if !defined(EVBARM_SPL_NOINLINE) 131 132 #define _splraise(ipl) iq80310_splraise(ipl) 133 #define _spllower(ipl) iq80310_spllower(ipl) 134 #define splx(spl) iq80310_splx(spl) 135 #ifdef __HAVE_FAST_SOFTINTS 136 void _setsoftintr(int); 137 #endif 138 139 #else 140 141 int _splraise(int); 142 int _spllower(int); 143 void splx(int); 144 #ifdef __HAVE_FAST_SOFTINTS 145 void _setsoftintr(int); 146 #endif 147 148 #endif /* ! EVBARM_SPL_NOINLINE */ 149 150 #endif /* _IQ80310_INTR_H_ */ 151