1/* $Id: imx23_olinuxino_start.S,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <machine/asm.h> 33#include <machine/pmap.h> 34#include <arm/armreg.h> 35#include <arm/imx/imx23var.h> 36#include <arm/imx/imx23_uartdbgreg.h> 37 38.section .start,"ax",%progbits 39 40.global _C_LABEL(olinuxino_start) 41_C_LABEL(olinuxino_start): 42 43 /* 44 * Set up the first level page table. The page table has 4096 section 45 * page table entries which each one maps 1MB of virtual memory. 46 * Section entries are mapped from mmu_init_table to the page table. 47 */ 48 l1pt_p .req r0 49 mit_p .req r1 50 va .req r2 51 pa .req r3 52 n_sec .req r4 53 attr .req r5 54 pte_p .req r6 55 sec .req r7 56 tmp .req r8 57 tmp2 .req r9 58 59 ldr l1pt_p, Ll1_pt 60 61 /* Zero the page table. */ 62 mov tmp, #0 63 add tmp2, l1pt_p, #L1_TABLE_SIZE 641: str tmp, [l1pt_p], #4 65 cmp l1pt_p, tmp2 66 blt 1b 67 68 ldr l1pt_p, Ll1_pt 69 70 /* Map sections. */ 71 ldr mit_p, =mmu_init_table 72 ldmia mit_p!, {va, pa, n_sec, attr} 73 74 /* 75 * Calculate PTE addresses for a MVA's. 76 * 77 * Bits[31:14] of the Translation Table Base register are concatenated 78 * with bits[31:20] of the modified virtual address and two zero bits 79 * to produce a physical address of the page table entry for a MVA: 80 * 81 * PTE = (TTBR & 0xffffc000) | ((MVA & 0xfff00000)>>18) 82 */ 833: ldr tmp, =0xffffc000 84 and pte_p, l1pt_p, tmp 85 ldr tmp, =0xfff00000 86 and va, va, tmp 87 mov va, va, LSR #18 88 orr pte_p, pte_p, va 89 902: orr sec, pa, attr 91 str sec, [pte_p], #4 /* Store #n_sec sections to the page */ 92 add pa, pa, #0x100000 /* table. */ 93 subs n_sec, #1 94 bne 2b 95 96 ldmia mit_p!, {va, pa, n_sec, attr} 97 cmp n_sec, #0 98 bne 3b 99 100 /* 101 * The Translation Table Base Register holds the physical address of 102 * the page table. 103 */ 104 mcr p15, 0, l1pt_p, c2, c0, 0 105 106 .unreq l1pt_p 107 .unreq mit_p 108 .unreq va 109 .unreq pa 110 .unreq n_sec 111 .unreq attr 112 .unreq pte_p 113 .unreq sec 114 .unreq tmp 115 .unreq tmp2 116 117 /* 118 * Sections are in domain 0 and we set D0 access control to client 119 * mode, which means AP bits are checked. Since we are running 120 * privileged mode and APs are kernel read/write, access is granted. 121 */ 122 mov r0, #DOMAIN_CLIENT<<(PMAP_DOMAIN_KERNEL*2) 123 mcr p15, 0, r0, c3, c0, 0 124 125 /* 126 * Enable the MMU. 127 */ 128 mov r0, #0 129 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB. */ 130 131 mrc p15, 0, r0, c1, c0, 0 132 ldr r1, =(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE \ 133 | CPU_CONTROL_AFLT_ENABLE | CPU_CONTROL_MMU_ENABLE) 134 orr r0, r0, r1 135 mcr p15, 0, r0, c1, c0, 0 136 nop /* Fetch flat. */ 137 nop /* Fetch flat. */ 138 139 /* 140 * Jump to start in locore.S. start sets the sp point to DRAM, zeroes 141 * the .bss and calls initarm. start never returns. 142 */ 143 ldr pc, =start 144 145 /* NOTREACHED */ 146 147/* 148 * Initial first level translation table on a 16kB boundary located at the 149 * end of the DRAM. 150 * 151 * The translation table has 4096 32-bit section entries, each describing 1MB of 152 * virtual memory which means 4GB of virtual memory to be addressed. 153 */ 154Ll1_pt: 155 .word (DRAM_BASE + MEMSIZE * 1024 * 1024 - L1_TABLE_SIZE) 156 157#define MMU_INIT(va,pa,n_sec,attr) \ 158 .word va; \ 159 .word pa; \ 160 .word n_sec; \ 161 .word attr; 162 163mmu_init_table: 164 /* On-chip RAM */ 165 MMU_INIT(0x00000000, 0x00000000, 166 1, 167 L1_S_AP(AP_KRW) | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_PROTO) 168 169 /* On-chip ROM (Vectors) */ 170 MMU_INIT(0xFFFF0000, 0xFFFF0000, 171 1, 172 L1_S_AP(AP_KRW) | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_PROTO) 173 174 /* DRAM */ 175 MMU_INIT(KERNEL_BASE_virt, KERNEL_BASE_phys, 176 MEMSIZE, 177 L1_S_AP(AP_KRW) | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_C |\ 178 L1_S_B | L1_S_PROTO) 179 180 /* Peripherals */ 181 MMU_INIT(APBH_BASE, APBH_BASE, 182 1, 183 L1_S_AP(AP_KRW) | L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_S_PROTO) 184 185 MMU_INIT(0, 0, 0, 0) 186