1 /* $Id: imx23_olinuxino_machdep.c,v 1.11 2020/11/28 14:02:30 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_arm_debug.h" 33 #include "opt_imx.h" 34 35 #include <sys/bus.h> 36 #include <sys/cdefs.h> 37 #include <sys/device.h> 38 #include <sys/mount.h> 39 #include <sys/reboot.h> 40 #include <sys/systm.h> 41 #include <sys/termios.h> 42 #include <sys/types.h> 43 44 #include <uvm/uvm_prot.h> 45 46 #include <machine/bootconfig.h> 47 #include <machine/db_machdep.h> 48 #include <machine/pmap.h> 49 50 #include <arm/armreg.h> 51 #include <arm/cpu.h> 52 #include <arm/cpufunc.h> 53 #include <arm/locore.h> 54 55 #include <arm/arm32/machdep.h> 56 #include <arm/arm32/pte.h> 57 58 #include <arm/imx/imx23_clkctrlreg.h> 59 #include <arm/imx/imx23_digctlreg.h> 60 #include <arm/imx/imx23_rtcreg.h> 61 #include <arm/imx/imx23_uartdbgreg.h> 62 #include <arm/imx/imx23var.h> 63 64 #include "plcom.h" 65 #if (NPLCOM > 0) 66 #include <evbarm/dev/plcomreg.h> 67 #include <evbarm/dev/plcomvar.h> 68 #endif 69 70 #include "opt_evbarm_boardtype.h" 71 #include "opt_machdep.h" 72 73 #define KERNEL_VM_BASE (KERNEL_BASE + 0x8000000) 74 #define KERNEL_VM_SIZE 0x20000000 75 76 #define L1_PAGE_TABLE (DRAM_BASE + MEMSIZE * 1024 * 1024 - L1_TABLE_SIZE) 77 #define BOOTIMX23_ARGS (L1_PAGE_TABLE - MAX_BOOT_STRING - 1) 78 79 #define PLCONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 80 #define PLCONSPEED 115200 81 82 #define REG_RD(reg) *(volatile uint32_t *)(reg) 83 #define REG_WR(reg, val) \ 84 do { \ 85 *(volatile uint32_t *)((reg)) = val; \ 86 } while (0) 87 88 #define KERNEL_BASE_PHYS ((paddr_t)&KERNEL_BASE_phys) 89 #define KERNEL_BASE_VIRT ((vaddr_t)&KERNEL_BASE_virt) 90 91 /* 92 * Static device map for i.MX23 peripheral address space. 93 */ 94 #define _A(a) ((a) & ~L1_S_OFFSET) 95 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 96 static const struct pmap_devmap devmap[] = { 97 { 98 _A(APBH_BASE), /* Virtual address. */ 99 _A(APBH_BASE), /* Physical address. */ 100 _S(APBH_SIZE + APBX_SIZE), /* APBX located after APBH. */ 101 VM_PROT_READ|VM_PROT_WRITE, /* Protection bits. */ 102 PTE_NOCACHE /* Cache attributes. */ 103 }, 104 { 0, 0, 0, 0, 0 } 105 }; 106 #undef _A 107 #undef _S 108 109 static struct plcom_instance imx23_pi = { 110 .pi_type = PLCOM_TYPE_PL011, 111 .pi_iot = &imx23_bus_space, 112 .pi_size = PL011COM_UART_SIZE, 113 .pi_iobase = HW_UARTDBG_BASE 114 }; 115 116 extern char KERNEL_BASE_phys; 117 extern char KERNEL_BASE_virt; 118 BootConfig bootconfig; 119 char *boot_args; 120 static char kernel_boot_args[MAX_BOOT_STRING]; 121 122 #define SSP_DIV 2 123 #define IO_FRAC 27 124 125 static void power_vddio_from_dcdc(int, int); 126 static void set_ssp_div(unsigned int); 127 static void set_io_frac(unsigned int); 128 static void bypass_ssp(void); 129 130 /* 131 * Initialize ARM and return new SVC stack pointer. 132 */ 133 vaddr_t 134 initarm(void *arg) 135 { 136 psize_t ram_size; 137 138 if (set_cpufuncs()) 139 panic("set_cpufuncs failed"); 140 141 kern_vtopdiff = KERNEL_BASE - KERNEL_BASE_PHYS; 142 143 pmap_devmap_register(devmap); 144 consinit(); 145 146 #define BDSTR(s) _BDSTR(s) 147 #define _BDSTR(s) #s 148 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 149 #undef BDSTR 150 #undef _BDSTR 151 152 /* 153 * SSP_CLK setup was postponed here from bootimx23 because SB wasn't 154 * able to load kernel if clocks were changed. 155 */ 156 power_vddio_from_dcdc(3300, 2925); 157 set_ssp_div(SSP_DIV); 158 set_io_frac(IO_FRAC); 159 bypass_ssp(); 160 161 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 162 163 /* Copy boot arguments passed from bootimx23. */ 164 boot_args = (char *)KERN_PHYSTOV(BOOTIMX23_ARGS); 165 memcpy(kernel_boot_args, boot_args, MAX_BOOT_STRING); 166 #ifdef BOOT_ARGS 167 strcpy(kernel_boot_args, BOOT_ARGS); 168 #endif 169 boot_args = kernel_boot_args; 170 #ifdef VERBOSE_INIT_ARM 171 printf("boot_args @ %lx: '%s'\n", KERN_PHYSTOV(BOOTIMX23_ARGS), 172 boot_args); 173 #endif 174 parse_mi_bootargs(boot_args); 175 176 ram_size = MEMSIZE * 1024 * 1024; 177 178 bootconfig.dramblocks = 1; 179 bootconfig.dram[0].address = DRAM_BASE; 180 bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 181 bootconfig.dram[0].flags = BOOT_DRAM_CAN_DMA | BOOT_DRAM_PREFER; 182 183 arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 184 ((vsize_t)&KERNEL_BASE_phys)); 185 186 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, 187 false); 188 189 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 190 } 191 192 /* 193 * Initialize console. 194 */ 195 void 196 consinit(void) 197 { 198 /* consinit() is called from also from the main(). */ 199 static int consinit_called = 0; 200 201 if (consinit_called) 202 return; 203 204 plcomcnattach(&imx23_pi, PLCONSPEED, IMX23_UART_CLK, PLCONMODE, 0); 205 206 consinit_called = 1; 207 208 return; 209 } 210 211 /* 212 * Reboot or halt the system. 213 */ 214 void 215 cpu_reboot(int howto, char *bootstr) 216 { 217 static int cpu_reboot_called = 0; 218 219 boothowto |= howto; 220 221 /* 222 * If this is the first invocation of cpu_reboot() and the RB_NOSYNC 223 * flag is not set in howto; sync and unmount the system disks by 224 * calling vfs_shutdown(9) and set the time of day clock by calling 225 * resettodr(9). 226 */ 227 if (!cpu_reboot_called && !(boothowto & RB_NOSYNC)) { 228 vfs_shutdown(); 229 resettodr(); 230 } 231 232 cpu_reboot_called = 1; 233 234 IRQdisable; /* FIQ's stays on because they are special. */ 235 236 /* 237 * If rebooting after a crash (i.e., if RB_DUMP is set in howto, but 238 * RB_HALT is not), save a system crash dump. 239 */ 240 if ((boothowto & RB_DUMP) && !(boothowto & RB_HALT)) { 241 panic("please implement crash dump!"); // XXX 242 for(;;); 243 /* NOTREACHED */ 244 } 245 246 /* Run any shutdown hooks by calling pmf_system_shutdown(9). */ 247 pmf_system_shutdown(boothowto); 248 249 printf("system %s.\n", boothowto & RB_HALT ? "halted" : "rebooted"); 250 251 if (boothowto & RB_HALT) { 252 /* Enable i.MX233 wait-for-interrupt mode. */ 253 REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU, 254 (REG_RD(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU) | 255 HW_CLKCTRL_CPU_INTERRUPT_WAIT)); 256 257 /* Disable FIQ's and wait for interrupt (which never arrives) */ 258 __asm volatile( \ 259 "mrs r0, cpsr\n\t" \ 260 "orr r0, #0x40\n\t" \ 261 "msr cpsr_c, r0\n\t" \ 262 "mov r0, #0\n\t" \ 263 "mcr p15, 0, r0, c7, c0, 4\n\t" 264 ); 265 266 for(;;); 267 268 /* NOT REACHED */ 269 } 270 271 /* Reboot the system. */ 272 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000); 273 REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN); 274 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0); 275 276 for(;;); 277 278 /* NOT REACHED */ 279 } 280 281 /* 282 * Delay us microseconds. 283 */ 284 void 285 delay(unsigned int us) 286 { 287 uint32_t start; 288 uint32_t now; 289 uint32_t elapsed; 290 uint32_t total; 291 uint32_t last; 292 293 total = 0; 294 last = 0; 295 start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 296 297 do { 298 now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 299 300 if (start <= now) 301 elapsed = now - start; 302 else /* Take care of overflow. */ 303 elapsed = (UINT32_MAX - start) + 1 + now; 304 305 total += elapsed - last; 306 last = elapsed; 307 308 } while (total < us); 309 310 return; 311 } 312 #include <arm/imx/imx23_powerreg.h> 313 #define PWR_VDDIOCTRL (HW_POWER_BASE + HW_POWER_VDDIOCTRL) 314 #define PWR_CTRL (HW_POWER_BASE + HW_POWER_CTRL) 315 #define PWR_CTRL_S (HW_POWER_BASE + HW_POWER_CTRL_SET) 316 #define PWR_CTRL_C (HW_POWER_BASE + HW_POWER_CTRL_CLR) 317 318 static void 319 power_vddio_from_dcdc(int target, int brownout) 320 { 321 uint32_t tmp_r; 322 323 /* BO_OFFSET must be withing 2700mV - 3475mV */ 324 if (brownout > 3475) 325 brownout = 3475; 326 else if (brownout < 2700) 327 brownout = 2700; 328 329 330 /* Set LINREG_OFFSET one step below TRG. */ 331 tmp_r = REG_RD(PWR_VDDIOCTRL); 332 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET; 333 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET); 334 REG_WR(PWR_VDDIOCTRL, tmp_r); 335 delay(10000); 336 337 /* Enable VDDIO switching converter output. */ 338 tmp_r = REG_RD(PWR_VDDIOCTRL); 339 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET; 340 REG_WR(PWR_VDDIOCTRL, tmp_r); 341 delay(10000); 342 343 /* Set target voltage and brownout level. */ 344 tmp_r = REG_RD(PWR_VDDIOCTRL); 345 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG); 346 tmp_r |= __SHIFTIN(((target - brownout) / 25), 347 HW_POWER_VDDIOCTRL_BO_OFFSET); 348 tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG); 349 REG_WR(PWR_VDDIOCTRL, tmp_r); 350 delay(10000); 351 352 /* Enable PWDN_BRNOUT. */ 353 REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ); 354 355 tmp_r = REG_RD(PWR_VDDIOCTRL); 356 tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT; 357 REG_WR(PWR_VDDIOCTRL, tmp_r); 358 359 return; 360 } 361 #include <arm/imx/imx23_clkctrlreg.h> 362 #define CLKCTRL_SSP (HW_CLKCTRL_BASE + HW_CLKCTRL_SSP) 363 #define CLKCTRL_FRAC (HW_CLKCTRL_BASE + HW_CLKCTRL_FRAC) 364 #define CLKCTRL_SEQ_C (HW_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_CLR) 365 366 static 367 void set_ssp_div(unsigned int div) 368 { 369 uint32_t tmp_r; 370 371 tmp_r = REG_RD(CLKCTRL_SSP); 372 tmp_r &= ~HW_CLKCTRL_SSP_CLKGATE; 373 REG_WR(CLKCTRL_SSP, tmp_r); 374 375 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 376 ; 377 378 tmp_r = REG_RD(CLKCTRL_SSP); 379 tmp_r &= ~HW_CLKCTRL_SSP_DIV; 380 tmp_r |= __SHIFTIN(div, HW_CLKCTRL_SSP_DIV); 381 REG_WR(CLKCTRL_SSP, tmp_r); 382 383 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 384 ; 385 386 return; 387 388 } 389 static 390 void set_io_frac(unsigned int frac) 391 { 392 uint8_t *io_frac; 393 uint32_t tmp_r; 394 395 io_frac = (uint8_t *)(CLKCTRL_FRAC); 396 io_frac++; /* emi */ 397 io_frac++; /* pix */ 398 io_frac++; /* io */ 399 tmp_r = (*io_frac)<<24; 400 tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATEIO | HW_CLKCTRL_FRAC_IOFRAC); 401 tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_IOFRAC); 402 403 *io_frac = (uint8_t)(tmp_r>>24); 404 405 return; 406 } 407 static 408 void bypass_ssp(void) 409 { 410 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP); 411 412 return; 413 } 414 415 416