1 /* $Id: imx23_olinuxino_machdep.c,v 1.3 2013/10/07 17:36:40 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/bus.h> 33 #include <sys/cdefs.h> 34 #include <sys/device.h> 35 #include <sys/mount.h> 36 #include <sys/reboot.h> 37 #include <sys/systm.h> 38 #include <sys/termios.h> 39 #include <sys/types.h> 40 41 #include <uvm/uvm_prot.h> 42 43 #include <machine/bootconfig.h> 44 #include <machine/db_machdep.h> 45 #include <machine/pmap.h> 46 47 #include <arm/armreg.h> 48 #include <arm/cpu.h> 49 #include <arm/cpufunc.h> 50 #include <arm/locore.h> 51 52 #include <arm/arm32/machdep.h> 53 #include <arm/arm32/pte.h> 54 55 #include <arm/imx/imx23_clkctrlreg.h> 56 #include <arm/imx/imx23_digctlreg.h> 57 #include <arm/imx/imx23_rtcreg.h> 58 #include <arm/imx/imx23_uartdbgreg.h> 59 #include <arm/imx/imx23var.h> 60 61 #include "plcom.h" 62 #if (NPLCOM > 0) 63 #include <evbarm/dev/plcomreg.h> 64 #include <evbarm/dev/plcomvar.h> 65 #endif 66 67 #include "opt_evbarm_boardtype.h" 68 69 #define KERNEL_VM_BASE (KERNEL_BASE + 0x8000000) 70 #define KERNEL_VM_SIZE 0x20000000 71 72 #define L1_PAGE_TABLE (DRAM_BASE + MEMSIZE * 1024 * 1024 - L1_TABLE_SIZE) 73 #define BOOTIMX23_ARGS (L1_PAGE_TABLE - MAX_BOOT_STRING - 1) 74 75 #define PLCONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 76 #define PLCONSPEED 115200 77 78 #define REG_RD(reg) *(volatile uint32_t *)(reg) 79 #define REG_WR(reg, val) \ 80 do { \ 81 *(volatile uint32_t *)((reg)) = val; \ 82 } while (0) 83 84 #define KERNEL_BASE_PHYS ((paddr_t)&KERNEL_BASE_phys) 85 #define KERNEL_BASE_VIRT ((vaddr_t)&KERNEL_BASE_virt) 86 #define KERN_VTOPHYS(va) \ 87 ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + KERNEL_BASE_PHYS)) 88 #define KERN_PHYSTOV(pa) \ 89 ((vaddr_t)((paddr_t)(pa) + KERNEL_BASE_VIRT + KERNEL_BASE)) 90 91 /* 92 * Static device map for i.MX23 peripheral address space. 93 */ 94 #define _A(a) ((a) & ~L1_S_OFFSET) 95 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 96 static const struct pmap_devmap devmap[] = { 97 { 98 _A(APBH_BASE), /* Virtual address. */ 99 _A(APBH_BASE), /* Physical address. */ 100 _S(APBH_SIZE + APBX_SIZE), /* APBX located after APBH. */ 101 VM_PROT_READ|VM_PROT_WRITE, /* Protection bits. */ 102 PTE_NOCACHE /* Cache attributes. */ 103 }, 104 { 0, 0, 0, 0, 0 } 105 }; 106 #undef _A 107 #undef _S 108 109 static struct plcom_instance imx23_pi = { 110 .pi_type = PLCOM_TYPE_PL011, 111 .pi_iot = &imx23_bus_space, 112 .pi_size = PL011COM_UART_SIZE, 113 .pi_iobase = HW_UARTDBG_BASE 114 }; 115 116 extern char KERNEL_BASE_phys; 117 extern char KERNEL_BASE_virt; 118 BootConfig bootconfig; 119 char *boot_args; 120 static char kernel_boot_args[MAX_BOOT_STRING]; 121 122 #define SSP_DIV 2 123 #define IO_FRAC 27 124 125 static void power_vddio_from_dcdc(int, int); 126 static void set_ssp_div(unsigned int); 127 static void set_io_frac(unsigned int); 128 static void bypass_ssp(void); 129 130 /* 131 * Initialize ARM and return new SVC stack pointer. 132 */ 133 u_int 134 initarm(void *arg) 135 { 136 psize_t ram_size; 137 138 if (set_cpufuncs()) 139 panic("set_cpufuncs failed"); 140 141 pmap_devmap_register(devmap); 142 consinit(); 143 144 #define BDSTR(s) _BDSTR(s) 145 #define _BDSTR(s) #s 146 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 147 #undef BDSTR 148 #undef _BDSTR 149 150 /* 151 * SSP_CLK setup was postponed here from bootimx23 because SB wasn't 152 * able to load kernel if clocks were changed. 153 */ 154 power_vddio_from_dcdc(3300, 2925); 155 set_ssp_div(SSP_DIV); 156 set_io_frac(IO_FRAC); 157 bypass_ssp(); 158 159 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 160 161 /* Copy boot arguments passed from bootimx23. */ 162 boot_args = (char *)KERN_PHYSTOV(BOOTIMX23_ARGS); 163 memcpy(kernel_boot_args, boot_args, MAX_BOOT_STRING); 164 boot_args = kernel_boot_args; 165 #ifdef VERBOSE_INIT_ARM 166 printf("boot_args @ %lx: '%s'\n", KERN_PHYSTOV(BOOTIMX23_ARGS), 167 boot_args); 168 #endif 169 parse_mi_bootargs(boot_args); 170 171 ram_size = MEMSIZE * 1024 * 1024; 172 173 bootconfig.dramblocks = 1; 174 bootconfig.dram[0].address = DRAM_BASE; 175 bootconfig.dram[0].pages = ram_size / PAGE_SIZE; 176 bootconfig.dram[0].flags = BOOT_DRAM_CAN_DMA | BOOT_DRAM_PREFER; 177 178 arm32_bootmem_init(bootconfig.dram[0].address, ram_size, 179 ((vsize_t)&KERNEL_BASE_phys)); 180 181 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, 182 true); 183 184 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 185 } 186 187 /* 188 * Initialize console. 189 */ 190 void 191 consinit(void) 192 { 193 /* consinit() is called from also from the main(). */ 194 static int consinit_called = 0; 195 196 if (consinit_called) 197 return; 198 199 plcomcnattach(&imx23_pi, PLCONSPEED, IMX23_UART_CLK, PLCONMODE, 0); 200 201 consinit_called = 1; 202 203 return; 204 } 205 206 /* 207 * Reboot or halt the system. 208 */ 209 void 210 cpu_reboot(int howto, char *bootstr) 211 { 212 static int cpu_reboot_called = 0; 213 214 boothowto |= howto; 215 216 /* 217 * If this is the first invocation of cpu_reboot() and the RB_NOSYNC 218 * flag is not set in howto; sync and unmount the system disks by 219 * calling vfs_shutdown(9) and set the time of day clock by calling 220 * resettodr(9). 221 */ 222 if (!cpu_reboot_called && !(boothowto & RB_NOSYNC)) { 223 vfs_shutdown(); 224 resettodr(); 225 } 226 227 cpu_reboot_called = 1; 228 229 IRQdisable; /* FIQ's stays on because they are special. */ 230 231 /* 232 * If rebooting after a crash (i.e., if RB_DUMP is set in howto, but 233 * RB_HALT is not), save a system crash dump. 234 */ 235 if ((boothowto & RB_DUMP) && !(boothowto & RB_HALT)) { 236 panic("please implement crash dump!"); // XXX 237 for(;;); 238 /* NOTREACHED */ 239 } 240 241 /* Run any shutdown hooks by calling pmf_system_shutdown(9). */ 242 pmf_system_shutdown(boothowto); 243 244 printf("system %s.\n", boothowto & RB_HALT ? "halted" : "rebooted"); 245 246 if (boothowto & RB_HALT) { 247 /* Enable i.MX233 wait-for-interrupt mode. */ 248 REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU, 249 (REG_RD(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU) | 250 HW_CLKCTRL_CPU_INTERRUPT_WAIT)); 251 252 /* Disable FIQ's and wait for interrupt (which never arrives) */ 253 __asm volatile( \ 254 "mrs r0, cpsr\n\t" \ 255 "orr r0, #0x40\n\t" \ 256 "msr cpsr_c, r0\n\t" \ 257 "mov r0, #0\n\t" \ 258 "mcr p15, 0, r0, c7, c0, 4\n\t" 259 ); 260 261 for(;;); 262 263 /* NOT REACHED */ 264 } 265 266 /* Reboot the system. */ 267 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000); 268 REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN); 269 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0); 270 271 for(;;); 272 273 /* NOT REACHED */ 274 } 275 276 /* 277 * Delay us microseconds. 278 */ 279 void 280 delay(unsigned int us) 281 { 282 uint32_t start; 283 uint32_t now; 284 uint32_t elapsed; 285 uint32_t total; 286 uint32_t last; 287 288 total = 0; 289 last = 0; 290 start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 291 292 do { 293 now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS); 294 295 if (start <= now) 296 elapsed = now - start; 297 else /* Take care of overflow. */ 298 elapsed = (UINT32_MAX - start) + 1 + now; 299 300 total += elapsed - last; 301 last = elapsed; 302 303 } while (total < us); 304 305 return; 306 } 307 #include <arm/imx/imx23_powerreg.h> 308 #define PWR_VDDIOCTRL (HW_POWER_BASE + HW_POWER_VDDIOCTRL) 309 #define PWR_CTRL (HW_POWER_BASE + HW_POWER_CTRL) 310 #define PWR_CTRL_S (HW_POWER_BASE + HW_POWER_CTRL_SET) 311 #define PWR_CTRL_C (HW_POWER_BASE + HW_POWER_CTRL_CLR) 312 313 static void 314 power_vddio_from_dcdc(int target, int brownout) 315 { 316 uint32_t tmp_r; 317 318 /* BO_OFFSET must be withing 2700mV - 3475mV */ 319 if (brownout > 3475) 320 brownout = 3475; 321 else if (brownout < 2700) 322 brownout = 2700; 323 324 325 /* Set LINREG_OFFSET one step below TRG. */ 326 tmp_r = REG_RD(PWR_VDDIOCTRL); 327 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET; 328 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET); 329 REG_WR(PWR_VDDIOCTRL, tmp_r); 330 delay(10000); 331 332 /* Enable VDDIO switching converter output. */ 333 tmp_r = REG_RD(PWR_VDDIOCTRL); 334 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET; 335 REG_WR(PWR_VDDIOCTRL, tmp_r); 336 delay(10000); 337 338 /* Set target voltage and brownout level. */ 339 tmp_r = REG_RD(PWR_VDDIOCTRL); 340 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG); 341 tmp_r |= __SHIFTIN(((target - brownout) / 25), 342 HW_POWER_VDDIOCTRL_BO_OFFSET); 343 tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG); 344 REG_WR(PWR_VDDIOCTRL, tmp_r); 345 delay(10000); 346 347 /* Enable PWDN_BRNOUT. */ 348 REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ); 349 350 tmp_r = REG_RD(PWR_VDDIOCTRL); 351 tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT; 352 REG_WR(PWR_VDDIOCTRL, tmp_r); 353 354 return; 355 } 356 #include <arm/imx/imx23_clkctrlreg.h> 357 #define CLKCTRL_SSP (HW_CLKCTRL_BASE + HW_CLKCTRL_SSP) 358 #define CLKCTRL_FRAC (HW_CLKCTRL_BASE + HW_CLKCTRL_FRAC) 359 #define CLKCTRL_SEQ_C (HW_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_CLR) 360 361 static 362 void set_ssp_div(unsigned int div) 363 { 364 uint32_t tmp_r; 365 366 tmp_r = REG_RD(CLKCTRL_SSP); 367 tmp_r &= ~HW_CLKCTRL_SSP_CLKGATE; 368 REG_WR(CLKCTRL_SSP, tmp_r); 369 370 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 371 ; 372 373 tmp_r = REG_RD(CLKCTRL_SSP); 374 tmp_r &= ~HW_CLKCTRL_SSP_DIV; 375 tmp_r |= __SHIFTIN(div, HW_CLKCTRL_SSP_DIV); 376 REG_WR(CLKCTRL_SSP, tmp_r); 377 378 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY) 379 ; 380 381 return; 382 383 } 384 static 385 void set_io_frac(unsigned int frac) 386 { 387 uint8_t *io_frac; 388 uint32_t tmp_r; 389 390 io_frac = (uint8_t *)(CLKCTRL_FRAC); 391 io_frac++; /* emi */ 392 io_frac++; /* pix */ 393 io_frac++; /* io */ 394 tmp_r = (*io_frac)<<24; 395 tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATEIO | HW_CLKCTRL_FRAC_IOFRAC); 396 tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_IOFRAC); 397 398 *io_frac = (uint8_t)(tmp_r>>24); 399 400 return; 401 } 402 static 403 void bypass_ssp(void) 404 { 405 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP); 406 407 return; 408 } 409 410 411