1 /* $NetBSD: ifpga_pcivar.h,v 1.2 2009/07/21 16:04:16 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 struct ifpga_pci_softc { 33 bus_space_tag_t sc_iot; 34 bus_space_handle_t sc_io_ioh; 35 bus_space_handle_t sc_conf_ioh; 36 37 bus_space_tag_t sc_memt; 38 bus_space_handle_t sc_app0_ioh; 39 bus_space_handle_t sc_app1_ioh; 40 bus_space_handle_t sc_reg_ioh; 41 }; 42 43 /* Apperture 0, 256MB normal cycles. */ 44 #define IFPGA_PCI_APP0_256MB_BASE 0x40000081 45 #define IFPGA_PCI_APP0_512MB_BASE 0x40000091 46 #define IFPGA_PCI_APP0_256MB_MAP 0x4006 47 48 /* Apperture 1, 256MB normal cycles, prefetchable. */ 49 #define IFPGA_PCI_APP1_256MB_BASE 0x50000081 50 #define IFPGA_PCI_APP1_256MB_MAP 0x5006 51 52 /* Apperture 1, 16MB configuration cycles. */ 53 #define IFPGA_PCI_APP1_CONF_BASE 0x61000041 54 #define IFPGA_PCI_APP1_CONF_T0_MAP 0x000a /* Type 0 cycle */ 55 #define IFPGA_PCI_APP1_CONF_T1_MAP 0x000b /* Type 1 cycle */ 56