1/* $NetBSD: hdlg_start.S,v 1.1 2006/04/16 02:22:33 nonaka Exp $ */ 2 3/* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <machine/asm.h> 39#include <arm/armreg.h> 40#include <arm/arm32/pte.h> 41 42 .section .start,"ax",%progbits 43 44 .global _C_LABEL(hdlg_start) 45_C_LABEL(hdlg_start): 46 /* 47 * We will go ahead and disable the MMU here so that we don't 48 * have to worry about flushing caches, etc. 49 * 50 * Note that we may not currently be running VA==PA, which means 51 * we'll need to leap to the next insn after disabing the MMU. 52 */ 53 adr r8, Lunmapped 54 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 55 orr r8, r8, #0xa0000000 /* OR in physical base address */ 56 57 mrc p15, 0, r2, c1, c0, 0 58 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 59 mcr p15, 0, r2, c1, c0, 0 60 61 nop 62 nop 63 nop 64 65 mov pc, r8 /* Heave-ho! */ 66 67Lunmapped: 68 /* reloc */ 69 adr r1, _C_LABEL(hdlg_start) 70 adr r0, .Lstart 71 ldmia r0, {r0, r2} 72 bic r0, r0, #0xff000000 73 orr r0, r0, #0xa0000000 74 bic r2, r2, #0xff000000 75 orr r2, r2, #0xa0000000 76 sub r2, r2, r0 /* size = _edata - start */ 77 cmp r1, r0 78 beq .Lreloc_done /* if (dst == src) */ 79 bcc .Lreloc_backwards 80 811: ldrb r3, [r1], #1 82 strb r3, [r0], #1 83 subs r2, r2, #1 84 bne 1b 85 b .Lreloc 86 87.Lreloc_backwards: 88 add r0, r0, r2 89 add r1, r1, r2 90 sub r0, r0, #1 91 sub r1, r1, #1 921: ldrb r3, [r1], #-1 93 strb r3, [r0], #-1 94 subs r2, r2, #1 95 bne 1b 96 97.Lreloc: 98 ldr r0, .Lreloc_done 99 bic r0, r0, #0xff000000 100 orr r0, r0, #0xa0000000 101 mov pc, r0 102 103.Lstart: 104 .word _C_LABEL(hdlg_start) 105 .word _edata 106 107.Lreloc_done: 108 .word Lreloc_done 109 110Lreloc_done: 111 /* 112 * We want to construct a memory map that maps us 113 * VA==PA (SDRAM at 0xa0000000) and also double-maps 114 * that space at 0xc0000000 (where the kernel address 115 * space starts). We create these mappings uncached 116 * and unbuffered to be safe. 117 * 118 * We also want to map the various devices we want to 119 * talk to VA==PA during bootstrap. 120 * 121 * We just use section mappings for all of this to make it easy. 122 * 123 * We will put the L1 table to do all this at 0xa0004000, which 124 * is also where RedBoot puts it. 125 */ 126 127 /* 128 * Step 1: Map the entire address space VA==PA. 129 */ 130 adr r0, Ltable 131 ldr r0, [r0] /* r0 = &l1table */ 132 133 mov r3, #(L1_S_AP(AP_KRW)) 134 orr r3, r3, #(L1_TYPE_S) 135 mov r2, #0x100000 /* advance by 1MB */ 136 mov r1, #0x1000 /* 4096MB */ 1371: 138 str r3, [r0], #0x04 139 add r3, r3, r2 140 subs r1, r1, #1 141 bgt 1b 142 143 /* 144 * Step 2: Map VA 0xc0000000->0xc7ffffff to PA 0xa0000000->0xa7ffffff. 145 */ 146 adr r0, Ltable /* r0 = &l1table */ 147 ldr r0, [r0] 148 149 mov r3, #(L1_S_AP(AP_KRW)) 150 orr r3, r3, #(L1_TYPE_S) 151 orr r3, r3, #0xa0000000 152 add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 153 mov r1, #0x80 /* 128MB */ 1541: 155 str r3, [r0], #0x04 156 add r3, r3, r2 157 subs r1, r1, #1 158 bgt 1b 159 160 /* OK! Page table is set up. Give it to the CPU. */ 161 adr r0, Ltable /* r0 = &l1table */ 162 ldr r0, [r0] 163 mcr p15, 0, r0, c2, c0, 0 164 165 /* Flush the old TLBs, just in case. */ 166 mcr p15, 0, r0, c8, c7, 0 167 168 /* Set the Domain Access register. Very important! */ 169 mov r0, #1 170 mcr p15, 0, r0, c3, c0, 0 171 172 /* Get ready to jump to the "real" kernel entry point... */ 173 ldr r0, Lstart 174 175 /* OK, let's enable the MMU. */ 176 mrc p15, 0, r2, c1, c0, 0 177 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 178 mcr p15, 0, r2, c1, c0, 0 179 180 nop 181 nop 182 nop 183 184 /* CPWAIT sequence to make sure the MMU is on... */ 185 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 186 mov r2, r2 /* force it to complete */ 187 mov pc, r0 /* leap to kernel entry point! */ 188 189Ltable: 190 .word 0xa0004000 191 192Lstart: 193 .word start 194