1/* $NetBSD: gumstix_start.S,v 1.13 2014/05/23 13:56:18 kiyohara Exp $ */ 2/* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33/* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62#include "opt_cputypes.h" 63#include "opt_gumstix.h" 64 65#include <machine/asm.h> 66#include <arm/armreg.h> 67#include "assym.h" 68 69RCSID("$NetBSD: gumstix_start.S,v 1.13 2014/05/23 13:56:18 kiyohara Exp $") 70 71/* 72 * CPWAIT -- Canonical method to wait for CP15 update. 73 * NOTE: Clobbers the specified temp reg. 74 * copied from arm/arm/cpufunc_asm_xscale.S 75 * XXX: better be in a common header file. 76 */ 77#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 78#define CPWAIT_BRANCH \ 79 sub pc, pc, #4 80#else 81#define CPWAIT_BRANCH 82#endif 83 84#define CPWAIT(tmp) \ 85 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ; \ 86 mov tmp, tmp /* wait for it to complete */ ; \ 87 CPWAIT_BRANCH /* branch to next insn */ 88 89/* 90 * Kernel start routine for GUMSTIX 91 * this code is excuted at the very first after the kernel is loaded 92 * by U-Boot. 93 */ 94 .text 95 96 .global _C_LABEL(gumstix_start) 97_C_LABEL(gumstix_start): 98 /* 99 * gumstix's loader is U-boot. it's running on RAM 100 */ 101 102 /* Our page table might be cached. Disable D-cache beforehand. */ 103 mrc p15, 0, r4, c1, c0, 0 104 bic r4, r4, #CPU_CONTROL_DC_ENABLE 105 mcr p15, 0, r4, c1, c0, 0 106 107 /* 108 * Kernel is loaded in SDRAM (0xa0200000..), and is expected to run 109 * in VA 0xc0200000.. (GUMSTIX) 110 * VA == PA if OVERO. 111 */ 112 113 /* save u-boot's args */ 114 adr r4, u_boot_args 115 nop 116 nop 117 nop 118 stmia r4!, {r0, r1, r2, r3} 119 nop 120 nop 121 nop 122 123 /* Calculate RAM size */ 124 adr r4, ram_size 125#if defined(GUMSTIX) 126 ldr r0, [r4] 127 128 mrc p15, 0, r1, c0, c0, 0 129 and r1, r1, #CPU_ID_XSCALE_COREGEN_MASK 130 cmp r1, #0x4000 131 bne 3f /* goto 3f, if basix or connex */ 1320: 133 /* check memory size, if verdex or verdex-pro */ 134 add r3, r4, r0 135 ldr r1, [r3] 136 cmp r0, r1 137 beq 2f 1381: 139 add r0, r0, r0 /* r0 <<= 1 */ 140 str r0, [r4] 141 b 0b 1422: 143 mvn r1, r1 /* r1 ^= 0xffffffff */ 144 str r1, [r3] 145 ldr r2, [r4] 146 cmp r1, r2 147 beq 3f 148 str r0, [r3] /* restore */ 149 b 1b 1503: 151#elif defined(OVERO) 152 mov r1, #0x7f000000 /* mask */ 153 orr r1, r1, #0x00e00000 /* mask */ 154 mov r3, #0x6d000000 /* OMAP34xx SDRC */ 155 add r3, r3, #0x0080 /* CS0 MCFG */ 156 ldr r2, [r3] 157 and r0, r1, r2, lsl #13 158 add r3, r3, #0x0030 /* CS1 MCFG */ 159 ldr r2, [r3] 160 and r2, r1, r2, lsl #13 161 add r0, r0, r2 162#endif 163 str r0, [r4] 164 165 /* Build page table from scratch */ 166 ldr r0, Lstartup_pagetable /* pagetable */ 167 adr r4, mmu_init_table 168 b 5f 169 1704: 171 str r3, [r0, r2, lsl #2] 172 add r2, r2, #1 173 add r3, r3, #(L1_S_SIZE) 174 adds r1, r1, #-1 175 bhi 4b 1765: 177 ldmia r4!, {r1, r2, r3} /* # of sections, PA|attr, VA */ 178 lsr r2, r2, #L1_S_SHIFT 179 cmp r1, #0 180 bne 4b 181 182 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 183 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 184 185#if defined(CPU_CORTEXA8) 186 mcr p15, 0, r0, c2, c0, 1 /* Set TTB1 */ 187 mov r0, #TTBCR_S_N_1 188 mcr p15, 0, r0, c2, c0, 2 /* Set TTBCR */ 189 mov r0, #0 190 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 191#endif 192 193 /* 194 * Set the Domain Access register. Very important! 195 * startup_pagetable puts to domain 0 now. 196 */ 197#define KERNEL_DOMAIN(x) ((x) << (PMAP_DOMAIN_KERNEL << 1)) 198 mov r0, #(KERNEL_DOMAIN(DOMAIN_CLIENT) | DOMAIN_CLIENT) 199 mcr p15, 0, r0, c3, c0, 0 200 201 /* Enable MMU and etc. */ 202 mrc p15, 0, r0, c1, c0, 0 203#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 204 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 205#endif 206#if defined(CPU_CORTEXA8) 207 /* Disable L2 cache beforehand. */ 208 mrc p15, 0, r1, c1, c0, 1 209 bic r1, r1, #0x2 /* clear L2EN */ 210 mcr p15, 0, r1, c1, c0, 1 211 212 orr r0, r0, #CPU_CONTROL_AFLT_ENABLE | CPU_CONTROL_DC_ENABLE 213 orr r0, r0, #CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_IC_ENABLE 214#endif 215 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 216 mcr p15, 0, r0, c1, c0, 0 217 /* 218 * Ensure that the coprocessor has finished turning on the MMU. 219 */ 220 CPWAIT(r0) 221 222 /* Jump to kernel code in TRUE VA */ 223 ldr r0, Lstart 224 bx r0 225 226Lstart: 227 .word start 228 229#ifndef STARTUP_PAGETABLE_ADDR 230#if defined(GUMSTIX) 231#define STARTUP_PAGETABLE_ADDR 0xa0000000 /* aligned 16kByte */ 232#elif defined(OVERO) 233#define STARTUP_PAGETABLE_ADDR 0x80000000 /* aligned 16kByte */ 234#endif 235#endif 236Lstartup_pagetable: 237 .word STARTUP_PAGETABLE_ADDR 238 239 .globl _C_LABEL(u_boot_args) 240u_boot_args: 241 .space 16 /* r0, r1, r2, r3 */ 242 243 .globl _C_LABEL(ram_size) 244ram_size: 245 .word 0x04000000 /* 64Mbyte */ 246 247 248#define MMU_INIT(va, pa, n_sec, attr) \ 249 .word n_sec ; \ 250 .word (va) ; \ 251 .word (pa) | (attr) ; 252 253mmu_init_table: 254#if defined(GUMSTIX) 255 /* fill all table VA==PA */ 256 MMU_INIT(0x00000000, 0x00000000, 257 1 << (32 - L1_S_SHIFT), L1_S_PROTO | L1_S_AP_KRW) 258 259#define SDRAM_START 0xa0000000 260 261 /* map SDRAM VA==PA, write-back cacheable (first 64M only)*/ 262 MMU_INIT(SDRAM_START, SDRAM_START, 263 64, L1_S_PROTO | L1_S_C | L1_S_AP_KRW) 264 265 /* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */ 266 MMU_INIT(0xc0000000, SDRAM_START, 267 64, L1_S_PROTO | L1_S_C | L1_S_AP_KRW) 268 269#elif defined(OVERO) 270 /* fill all table VA==PA */ 271 MMU_INIT(0x00000000, 0x00000000, 272 1 << (32 - L1_S_SHIFT), L1_S_PROTO | L1_S_APv7_KRW) 273 274#define SDRAM_START 0x80000000 275 276 /* Map VA to PA, write-back cacheable (first 64M only) */ 277 MMU_INIT(KERNEL_BASE & 0xffffffff, SDRAM_START, 278 64, L1_S_PROTO | L1_S_B | L1_S_C | L1_S_APv7_KRW) 279#endif 280 281 MMU_INIT(0, 0, 0, 0) /* end of table */ 282