xref: /netbsd-src/sys/arch/evbarm/gumstix/gumstix_start.S (revision 0df165c04d0a9ca1adde9ed2b890344c937954a6)
1/*	$NetBSD: gumstix_start.S,v 1.5 2007/10/17 19:54:12 garbled Exp $ */
2/*
3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
4 * All rights reserved.
5 *
6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM
7 * Corporation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the project nor the name of SOUM Corporation
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS''
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33/*
34 * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
35 * Written by Hiroyuki Bessho for Genetec Corporation.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 *    notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 *    notice, this list of conditions and the following disclaimer in the
44 *    documentation and/or other materials provided with the distribution.
45 * 3. The name of Genetec Corporation may not be used to endorse or
46 *    promote products derived from this software without specific prior
47 *    written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
52 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
59 * POSSIBILITY OF SUCH DAMAGE.
60 */
61
62#include <machine/asm.h>
63#include <arm/armreg.h>
64#include <arm/arm32/pte.h>
65#include <arm/arm32/pmap.h>		/* for PMAP_DOMAIN_KERNEL */
66
67#ifndef SDRAM_START
68#define SDRAM_START	0xa0000000
69#endif
70
71/*
72 * CPWAIT -- Canonical method to wait for CP15 update.
73 * NOTE: Clobbers the specified temp reg.
74 * copied from arm/arm/cpufunc_asm_xscale.S
75 * XXX: better be in a common header file.
76 */
77#define	CPWAIT_BRANCH							 \
78	sub	pc, pc, #4
79
80#define	CPWAIT(tmp)							 \
81	mrc	p15, 0, tmp, c2, c0, 0	/* arbitrary read of CP15 */	;\
82	mov	tmp, tmp		/* wait for it to complete */	;\
83	CPWAIT_BRANCH			/* branch to next insn */
84
85/*
86 * Kernel start routine for GUMSTIX
87 * this code is excuted at the very first after the kernel is loaded
88 * by U-Boot.
89 */
90	.text
91
92	.global	_C_LABEL(gumstix_start)
93_C_LABEL(gumstix_start):
94	/* gumstix's loader is u-boot.  it's running on RAM */
95	/*
96	 *  Kernel is loaded in SDRAM (0xa0200000..), and is expected to run
97	 *  in VA 0xc0200000..
98	 */
99	/* save u-boot's args */
100	adr	r0, u_boot_args
101	nop
102	nop
103	nop
104	stmia	r0!, {r3, r4, r5, r6}
105	nop
106	nop
107	nop
108
109	/* build page table from scratch */
110	ldr	r0, Lstartup_pagetable		/* pagetable */
111	adr	r4, mmu_init_table
112	b	3f
113
1142:
115	str	r3, [r0, r2]
116	add	r2, r2, #4
117	add	r3, r3, #(L1_S_SIZE)
118	adds	r1, r1, #-1
119	bhi	2b
1203:
121	ldmia	r4!, {r1, r2, r3}	/* # of sections, PA|attr, VA */
122	cmp	r1, #0
123	bne	2b
124
125	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
126	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
127
128	/* Set the Domain Access register.  Very important! */
129        mov     r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
130	mcr	p15, 0, r0, c3, c0, 0
131
132	/* Enable MMU */
133	mrc	p15, 0, r0, c1, c0, 0
134	orr	r0, r0, #CPU_CONTROL_SYST_ENABLE
135	orr	r0, r0, #CPU_CONTROL_MMU_ENABLE
136	mcr	p15, 0, r0, c1, c0, 0
137	CPWAIT(r0)
138
139	/* Jump to kernel code in TRUE VA */
140	adr	r0, Lstart
141	ldr	pc, [r0]
142
143Lstart:
144	.word	start
145
146#ifndef STARTUP_PAGETABLE_ADDR
147#define STARTUP_PAGETABLE_ADDR 0xa0000000	/* aligned 16kByte */
148#endif
149Lstartup_pagetable:
150	.word	STARTUP_PAGETABLE_ADDR
151
152	.globl	_C_LABEL(u_boot_args)
153u_boot_args:
154	.space	16			/* r3, r4, r5, r6 */
155
156
157#define MMU_INIT(va,pa,n_sec,attr) \
158	.word	n_sec					    ; \
159	.word	4 * ((va) >> L1_S_SHIFT)		    ; \
160	.word	(pa) | (attr)				    ;
161
162mmu_init_table:
163	/* fill all table VA==PA */
164	MMU_INIT(0x00000000, 0x00000000,
165	    1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP(AP_KRW))
166
167	/* map SDRAM VA==PA, WT cacheable */
168	MMU_INIT(SDRAM_START, SDRAM_START,
169	    64, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW))
170
171	/* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */
172	MMU_INIT(0xc0000000, SDRAM_START,
173	    64, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW))
174
175	.word	0			/* end of table */
176