1 /* $NetBSD: plcomreg.h,v 1.5 2012/10/24 21:23:45 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 33 #define PLCOM_FREQ 1843200 /* 16-bit baud rate divisor */ 34 #define PLCOM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 35 36 /* control register */ 37 #define PL011_CR_CTSEN 0x8000 /* CTS HW flow control enable */ 38 #define PL011_CR_RTSEN 0x4000 /* RTS HW flow control enable */ 39 #define PL011_CR_OUT2 0x2000 /* Complement of UART Out2 MSR */ 40 #define PL011_CR_OUT1 0x1000 /* Complement of UART Out1 MSR */ 41 #define PL011_CR_RTS 0x0800 /* Request to send */ 42 #define PL011_CR_DTR 0x0400 /* Data transmit Ready */ 43 #define PL011_CR_RXE 0x0200 /* Receive enable */ 44 #define PL011_CR_TXE 0x0100 /* Transmit enable */ 45 #define PL01X_CR_LBE 0x0080 /* Loopback enable */ 46 #define PL010_CR_RTIE 0x0040 /* Receive timeout interrupt enable */ 47 #define PL010_CR_TIE 0x0020 /* Transmit interrupt enable */ 48 #define PL010_CR_RIE 0x0010 /* Receive interrrupt enable */ 49 #define PL010_CR_MSIE 0x0008 /* Modem status interrupt enable */ 50 #define PL01X_CR_SIRLP 0x0004 /* IrDA SIR Low power mode */ 51 #define PL01X_CR_SIREN 0x0002 /* SIR Enable */ 52 #define PL01X_CR_UARTEN 0x0001 /* Uart enable */ 53 54 /* interrupt identification register */ 55 #define PL010_IIR_RTIS 0x08 56 #define PL010_IIR_TIS 0x04 57 #define PL010_IIR_RIS 0x02 58 #define PL010_IIR_MIS 0x01 59 #define PL010_IIR_IMASK \ 60 (PL010_IIR_RTIS | PL010_IIR_TIS | PL010_IIR_RIS | PL010_IIR_MIS) 61 62 /* line control register */ 63 #define PL011_LCR_SPS 0x80 /* Stick parity select */ 64 #define PL01X_LCR_WLEN 0x60 /* Mask of size bits */ 65 #define PL01X_LCR_8BITS 0x60 /* 8 bits per serial word */ 66 #define PL01X_LCR_7BITS 0x40 /* 7 bits */ 67 #define PL01X_LCR_6BITS 0x20 /* 6 bits */ 68 #define PL01X_LCR_5BITS 0x00 /* 5 bits */ 69 #define PL01X_LCR_FEN 0x10 /* FIFO enable */ 70 #define PL01X_LCR_STP2 0x08 /* 2 stop bits per serial word */ 71 #define PL01X_LCR_EPS 0x04 /* Even parity select */ 72 #define PL01X_LCR_PEN 0x02 /* Parity enable */ 73 #define PL01X_LCR_PEVEN (PL01X_LCR_PEN | PL01X_LCR_EPS) 74 #define PL01X_LCR_PODD PL01X_LCR_PEN 75 #define PL01X_LCR_PNONE 0x00 /* No parity */ 76 #define PL01X_LCR_BRK 0x01 /* Break Control */ 77 78 /* modem control register */ 79 #define PL01X_MCR_RTS 0x02 /* Request To Send */ 80 #define PL01X_MCR_DTR 0x01 /* Data Terminal Ready */ 81 #define PL011_MCR(mcr) ((mcr) << 10) /* MCR to CR bit values for PL011 */ 82 83 /* receive status register */ 84 #define PL01X_RSR_OE 0x08 /* Overrun Error */ 85 #define PL01X_RSR_BE 0x04 /* Break */ 86 #define PL01X_RSR_PE 0x02 /* Parity Error */ 87 #define PL01X_RSR_FE 0x01 /* Framing Error */ 88 #define PL01X_RSR_ERROR \ 89 (PL01X_RSR_OE | PL01X_RSR_BE | PL01X_RSR_PE | PL01X_RSR_FE) 90 91 /* flag register */ 92 #define PL011_FR_RI 0x100 /* Ring Indicator */ 93 #define PL01X_FR_TXFE 0x080 /* Transmit fifo empty */ 94 #define PL01X_FR_RXFF 0x040 /* Recive fifo full */ 95 #define PL01X_FR_TXFF 0x020 /* Transmit fifo full */ 96 #define PL01X_FR_RXFE 0x010 /* Receive fifo empty */ 97 #define PL01X_FR_BUSY 0x008 /* Uart Busy */ 98 #define PL01X_FR_DCD 0x004 /* Data carrier detect */ 99 #define PL01X_FR_DSR 0x002 /* Data set ready */ 100 #define PL01X_FR_CTS 0x001 /* Clear to send */ 101 102 /* modem status register */ 103 /* All deltas are from the last read of the MSR. */ 104 #define PL01X_MSR_DCD PL01X_FR_DCD 105 #define PL01X_MSR_DSR PL01X_FR_DSR 106 #define PL01X_MSR_CTS PL01X_FR_CTS 107 #define PL011_MSR_RI PL011_FR_RI 108 109 /* ifls */ 110 #define PL011_IFLS_1EIGHTH 0 111 #define PL011_IFLS_1QUARTER 1 112 #define PL011_IFLS_1HALF 2 113 #define PL011_IFLS_3QUARTERS 3 114 #define PL011_IFLS_7EIGHTHS 4 115 #define PL011_IFLS_RXIFLS(x) (((x) & 0x7) << 3) 116 #define PL011_IFLS_TXIFLS(x) (((x) & 0x7) << 0) 117 118 /* All interrupt status/clear registers */ 119 #define PL011_INT_OE 0x400 120 #define PL011_INT_BE 0x200 121 #define PL011_INT_PE 0x100 122 #define PL011_INT_FE 0x080 123 #define PL011_INT_RT 0x040 124 #define PL011_INT_TX 0x020 125 #define PL011_INT_RX 0x010 126 #define PL011_INT_DSR 0x008 127 #define PL011_INT_DCD 0x004 128 #define PL011_INT_CTS 0x002 129 #define PL011_INT_RIR 0x001 130 #define PL011_INT_MSMASK \ 131 (PL011_INT_DSR | PL011_INT_DCD | PL011_INT_CTS | PL011_INT_RIR) 132 133 #define PL011_INT_ALLMASK \ 134 (PL011_INT_RT | PL011_INT_TX | PL011_INT_RX | PL011_INT_MSMASK) 135 136 137 /* DMA control registers */ 138 #define PL011_DMA_ONERR 0x4 139 #define PL011_DMA_TXE 0x2 140 #define PL011_DMA_RXE 0x1 141 142 /* Register offsets */ 143 #define PL01XCOM_DR 0x00 /* Data Register */ 144 #define PL01XCOM_RSR 0x04 /* Receive status register */ 145 #define PL01XCOM_ECR 0x04 /* Error clear register - same as RSR */ 146 #define PL010COM_LCR 0x08 /* Line Control Register */ 147 #define PL010COM_DLBH 0x0c 148 #define PL010COM_DLBL 0x10 149 #define PL010COM_CR 0x14 150 #define PL01XCOM_FR 0x18 /* Flag Register */ 151 #define PL010COM_IIR 0x1c 152 #define PL010COM_ICR 0x1c 153 #define PL01XCOM_ILPR 0x20 /* IrDA low-power control register */ 154 #define PL011COM_IBRD 0x24 /* Integer baud rate divisor register */ 155 #define PL011COM_FBRD 0x28 /* Fractional baud rate divisor register */ 156 #define PL011COM_LCRH 0x2c /* Line control register */ 157 #define PL011COM_CR 0x30 /* Control register */ 158 #define PL011COM_IFLS 0x34 /* Interrupt FIFO level select register */ 159 #define PL011COM_IMSC 0x38 /* Interrupt mask set/clear register */ 160 #define PL011COM_RIS 0x3c /* Raw interrupt status register */ 161 #define PL011COM_MIS 0x40 /* Masked interrupt status register */ 162 #define PL011COM_ICR 0x44 /* Interrupt clear register register */ 163 #define PL011COM_DMACR 0x48 /* DMA control register register */ 164 165 #define PL010COM_UART_SIZE 0x100 166 #define PL011COM_UART_SIZE 0x1000 167