1/* $NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $ */ 2/******************************************************************************* 3Copyright (C) Marvell International Ltd. and its affiliates 4 5Developed by Semihalf 6 7******************************************************************************** 8Marvell BSD License 9 10If you received this File from Marvell, you may opt to use, redistribute and/or 11modify this File under the following licensing terms. 12Redistribution and use in source and binary forms, with or without modification, 13are permitted provided that the following conditions are met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in the 20 documentation and/or other materials provided with the distribution. 21 22 * Neither the name of Marvell nor the names of its contributors may be 23 used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 27ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 30ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 33ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 37*******************************************************************************/ 38 39#include "opt_cputypes.h" 40 41#include <machine/asm.h> 42#include <arm/armreg.h> 43#include <evbarm/marvell/marvellreg.h> 44#include <evbarm/marvell/marvellvar.h> 45#include "assym.h" 46 47RCSID("$NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $") 48 49#ifdef KERNEL_BASES_EQUAL 50#error KERNEL_BASE_VIRT should not equal KERNEL_BASE_PHYS 51#endif 52 53/* 54 * We don't want to hard-code some basic things like RAM start etc. 55 * Hence, it is important to set the following options to resanoable values 56 * in std.armadaxp configuration file. 57 */ 58#if !defined(STARTUP_PAGETABLE_ADDR) 59#error STARTUP_PAGETABLE_ADDR not defined. Please define it in std.armadaxp 60#elif !defined(MEMSTART) 61#error MEMSTART not defined. Please define it in std.armadaxp 62#endif 63 64 .section .start,"ax",%progbits 65 66 .global _C_LABEL(armadaxp_start) 67_C_LABEL(armadaxp_start): 68 /* Move into supervisor mode and disable IRQs/FIQs. */ 69 cpsid if, #PSR_SVC32_MODE 70 71 /* Disable MMU for a while */ 72 mrc p15, 0, r2, c1, c0, 0 73 movw r1, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ 74 CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_IC_ENABLE |\ 75 CPU_CONTROL_BPRD_ENABLE) 76 bic r2, r2, r1 77 mcr p15, 0, r2, c1, c0, 0 78 dsb 79 isb 80 81 /* build page table from scratch */ 82 movw r0, #:lower16:STARTUP_PAGETABLE_ADDR 83 movt r0, #:upper16:STARTUP_PAGETABLE_ADDR 84 adr r4, mmu_init_table 85 b 3f 86 872: str r3, [r0, r2] 88 add r2, r2, #4 89 add r3, r3, #(L1_S_SIZE) 90 adds r1, r1, #-1 91 bhi 2b 923: 93 ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */ 94 cmp r1, #0 95 bne 2b 96 97 mcr p15, 0, r0, c2, c0, 0 // Set TTBR0 98#ifdef ARM_MMU_EXTENDED 99 mcr p15, 0, r0, c2, c0, 1 // Set TTBR1 100 mov r0, #TTBCR_S_N_1 101#else 102 mov r0, #0 103#endif 104 mcr p15, 0, r0, c2, c0, 2 // TTBCR write 105 106 mov r0, #0 107 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 108 109 mcr p15, 0, r0, c13, c0, 1 // CONTEXTIDR write: Set ASID to 0 110 111 /* Set the Domain Access register. Very important! */ 112 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 113 mcr p15, 0, r0, c3, c0, 0 // DACR write 114 115#define CPU_CONTROL_SET (CPU_CONTROL_XP_ENABLE | CPU_CONTROL_IC_ENABLE \ 116 | CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) 117 118 /* Enable MMU */ 119 mrc p15, 0, r0, c1, c0, 0 120 movw r1, #:lower16:CPU_CONTROL_SET 121#if (CPU_CONTROL_SET & 0xffff) != 0 122 movt r1, #:upper16:CPU_CONTROL_SET 123#endif 124 orr r0, r0, r1 125 mcr p15, 0, r0, c1, c0, 0 126 isb 127 dsb 128 129 /* Jump to kernel code in TRUE VA */ 130 movw ip, #:lower16:start 131 movt ip, #:upper16:start 132 bx ip 133 134 /* NOTREACHED */ 135 136#define MMU_INIT(va,pa,n_sec,attr) \ 137 .word n_sec ; \ 138 .word 4*((va)>>L1_S_SHIFT) ; \ 139 .word (pa)|(attr) ; 140 141mmu_init_table: 142 /* fill all table VA==PA */ 143 /* map SDRAM VA==PA, WT cacheable */ 144 MMU_INIT(MEMSTART, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 145 146 /* map VA 0x80000000..0x83ffffff to PA */ 147 MMU_INIT(KERNEL_BASE_EXT, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 148 149 /* 150 * In case of early start debugging it might be useful to map 151 * SoC registers (for UART access). 152 */ 153 MMU_INIT(MARVELL_INTERREGS_PBASE, MARVELL_INTERREGS_PBASE, 1, 154 L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW) 155 MMU_INIT(MARVELL_INTERREGS_VBASE, MARVELL_INTERREGS_PBASE, 1, 156 L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW) 157 158 /* end of table */ 159 MMU_INIT(0, 0, 0, 0) 160