1/* $NetBSD: armadaxp_start.S,v 1.2 2013/05/29 23:50:34 rkujawa Exp $ */ 2/******************************************************************************* 3Copyright (C) Marvell International Ltd. and its affiliates 4 5Developed by Semihalf 6 7******************************************************************************** 8Marvell BSD License 9 10If you received this File from Marvell, you may opt to use, redistribute and/or 11modify this File under the following licensing terms. 12Redistribution and use in source and binary forms, with or without modification, 13are permitted provided that the following conditions are met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in the 20 documentation and/or other materials provided with the distribution. 21 22 * Neither the name of Marvell nor the names of its contributors may be 23 used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 27ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 30ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 33ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 37*******************************************************************************/ 38 39#include "opt_cputypes.h" 40 41#include <machine/asm.h> 42#include <arm/armreg.h> 43#include <arm/arm32/pmap.h> 44 45RCSID("$NetBSD: armadaxp_start.S,v 1.2 2013/05/29 23:50:34 rkujawa Exp $") 46 47#define CPWAIT_BRANCH \ 48 sub pc, pc, #4 49 50#define CPWAIT(tmp) \ 51 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 52 mov tmp, tmp /* wait for it to complete */ ;\ 53 CPWAIT_BRANCH /* branch to next insn */ 54 55/* 56 * We don't want to hard-code some basic things like RAM start etc. 57 * Hence, it is important to set the following options to resanoable values 58 * in std.armadaxp configuration file. 59 */ 60#if !defined(STARTUP_PAGETABLE_ADDR) 61#error STARTUP_PAGETABLE_ADDR not defined. Please define it in std.armadaxp 62#elif !defined(MEMSTART) 63#error MEMSTART not defined. Please define it in std.armadaxp 64#endif 65 66 .text 67 68 .global _C_LABEL(armadaxp_start) 69_C_LABEL(armadaxp_start): 70 /* Move into supervisor mode and disable IRQs/FIQs. */ 71 mrs r0, cpsr 72 bic r0, r0, #PSR_MODE 73 orr r0, r0, #(I32_bit | F32_bit) 74 msr cpsr_c, r0 75 76 adr r7, Lunmapped 77 bic r7, r7, #0xf0000000 78 orr r7, r7, #MEMSTART 79disable_mmu: 80 /* Disable MMU for a while */ 81 mrc p15, 0, r2, c1, c0, 0 82 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ 83 CPU_CONTROL_WBUF_ENABLE) 84 bic r2, r2, #(CPU_CONTROL_IC_ENABLE) 85 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE) 86 mcr p15, 0, r2, c1, c0, 0 87 88 nop 89 nop 90 nop 91 mov pc, r7 92Lunmapped: 93 /* build page table from scratch */ 94 ldr r0, Lstartup_pagetable 95 adr r4, mmu_init_table 96 b 3f 97 982: 99 str r3, [r0, r2] 100 add r2, r2, #4 101 add r3, r3, #(L1_S_SIZE) 102 adds r1, r1, #-1 103 bhi 2b 1043: 105 ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */ 106 cmp r1, #0 107 adrne r5, 2b 108 bicne r5, r5, #0xf0000000 109 orrne r5, r5, #MEMSTART 110 movne pc, r5 111 112 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 113 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 114 115 mov r0, #0 116 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 117 118 /* Set the Domain Access register. Very important! */ 119 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 120 mcr p15, 0, r0, c3, c0, 0 121 122 /* Enable MMU */ 123 mrc p15, 0, r0, c1, c0, 0 124 orr r0, r0, #CPU_CONTROL_XP_ENABLE 125 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) 126 mcr p15, 0, r0, c1, c0, 0 127 nop 128 nop 129 nop 130 CPWAIT(r0) 131 132 /* Jump to kernel code in TRUE VA */ 133 adr r0, Lstart 134 ldr pc, [r0] 135Lstart: 136 .word start 137 138 /* NOTREACHED */ 139Lstartup_pagetable: 140 .word STARTUP_PAGETABLE_ADDR 141 142#define MMU_INIT(va,pa,n_sec,attr) \ 143 .word n_sec ; \ 144 .word 4*((va)>>L1_S_SHIFT) ; \ 145 .word (pa)|(attr) ; 146 147mmu_init_table: 148 /* fill all table VA==PA */ 149 /* map SDRAM VA==PA, WT cacheable */ 150 MMU_INIT(0, 0, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 151 /* map VA 0xc0000000..0xc3ffffff to PA */ 152 MMU_INIT(0xc0000000, 0, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 153 /* 154 * In case of early start debugging it might be useful to map 155 * SoC registers (for UART access). 156 */ 157 MMU_INIT(0xd0000000, 0xd0000000, 1, L1_TYPE_S|L1_S_PROTO|L1_S_AP(AP_KRW)) 158 /* end of table */ 159 MMU_INIT(0, 0, 0, 0) 160