1/* $NetBSD: brh_start.S,v 1.1 2003/01/25 02:00:17 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#include <machine/asm.h> 39#include <arm/armreg.h> 40#include <arm/arm32/pte.h> 41 42#include <arm/xscale/beccreg.h> 43 44#include <evbarm/adi_brh/brhreg.h> 45 46 .section .start,"ax",%progbits 47 48 .global _C_LABEL(brh_start) 49_C_LABEL(brh_start): 50 /* 51 * Get a pointer to the LED (physical address). 52 */ 53 mov ip, #(BRH_LED_BASE) 54 55 /* 56 * We will go ahead and disable the MMU here so that we don't 57 * have to worry about flushing caches, etc. 58 * 59 * Note that we may not currently be running VA==PA, which means 60 * we'll need to leap to the next insn after disabing the MMU. 61 */ 62 add r8, pc, #(.Lunmapped - . - 8) 63 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 64 orr r8, r8, #0xc0000000 /* OR in physical base address */ 65 66 mrc p15, 0, r2, c1, c0, 0 67 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 68 mcr p15, 0, r2, c1, c0, 0 69 70 nop 71 nop 72 nop 73 74 mov pc, r8 /* Heave-ho! */ 75 76.Lunmapped: 77 /* 78 * We want to construct a memory map that maps us 79 * VA==PA (SDRAM at 0xc0000000) (which also happens 80 * to be where the kernel address space starts). 81 * We create these mappings uncached and unbuffered 82 * to be safe. 83 * 84 * We also map various devices at their expected locations, 85 * because we will need to talk to them during bootstrap. 86 * 87 * We just use section mappings for all of this to make it easy. 88 * 89 * We will put the L1 table to do all this at 0xc0004000. 90 */ 91 92 93 /* 94 * Step 1: Map the entire address space VA==PA. 95 */ 96 add r0, pc, #(.Ltable - . - 8) 97 ldr r0, [r0] /* r0 = &l1table */ 98 99 mov r3, #(L1_S_AP(AP_KRW)) 100 orr r3, r3, #(L1_TYPE_S) 101 mov r2, #0x100000 /* advance by 1MB */ 102 mov r1, #0x1000 /* 4096MB */ 1031: 104 str r3, [r0], #0x04 105 add r3, r3, r2 106 subs r1, r1, #1 107 bgt 1b 108 109#if 0 110 /* 111 * Step 2: Map the PCI configuration space (this is needed 112 * to access some of the core logic registers). 113 */ 114 add r0, pc, #(.Ltable - . - 8) /* r0 = &l1table */ 115 ldr r0, [r0] 116 117 mov r3, #(L1_S_AP(AP_KRW)) 118 orr r3, r3, #(L1_TYPE_S) 119 orr r3, r3, #(BECC_PCI_CONF_BASE) 120 add r0, r0, #((BRH_PCI_CONF_VBASE >> L1_S_SHIFT) * 4) 121 mov r1, #(BRH_PCI_CONF_VSIZE >> L1_S_SHIFT) 1221: 123 str r3, [r0], #0x04 124 add r3, r3, r2 125 subs r1, r1, #1 126 bgt 1b 127#endif 128 129 /* 130 * Step 3: Map the BECC, UARTs, and LED display. 131 */ 132 add r0, pc, #(.Ltable - . - 8) /* r0 = &l1table */ 133 ldr r0, [r0] 134 135 mov r3, #(L1_S_AP(AP_KRW)) 136 orr r3, r3, #(L1_TYPE_S) 137 138 orr r3, r3, #(BECC_REG_BASE) 139 add r2, pc, #(.Lbrh_becc_vbase - . - 8) 140 ldr r2, [r2] 141 str r3, [r0, r2] 142 bic r3, r3, #(BECC_REG_BASE) 143 144 orr r3, r3, #(BRH_UART1_BASE) 145 add r2, pc, #(.Lbrh_uart1_vbase - . - 8) 146 ldr r2, [r2] 147 str r3, [r0, r2] 148 bic r3, r3, #(BRH_UART1_BASE) 149 150 orr r3, r3, #(BRH_UART2_BASE) 151 add r2, pc, #(.Lbrh_uart2_vbase - . - 8) 152 ldr r2, [r2] 153 str r3, [r0, r2] 154 bic r3, r3, #(BRH_UART2_BASE) 155 156 orr r3, r3, #(BRH_LED_BASE) 157 add r2, pc, #(.Lbrh_led_vbase - . - 8) 158 ldr r2, [r2] 159 str r3, [r0, r2] 160 bic r3, r3, #(BRH_LED_BASE) 161 162 /* OK! Page table is set up. Give it to the CPU. */ 163 add r0, pc, #(.Ltable - . - 8) 164 ldr r0, [r0] 165 mcr p15, 0, r0, c2, c0, 0 166 167 /* Flush the old TLBs, just in case. */ 168 mcr p15, 0, r0, c8, c7, 0 169 170 /* Set the Domain Access register. Very important! */ 171 mov r0, #1 172 mcr p15, 0, r0, c3, c0, 0 173 174 /* Get ready to jump to the "real" kernel entry point... */ 175 add r0, pc, #(.Lstart - . - 8) 176 ldr r0, [r0] 177 178 /* OK, let's enable the MMU. */ 179 mrc p15, 0, r2, c1, c0, 0 180 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 181 mcr p15, 0, r2, c1, c0, 0 182 183 nop 184 nop 185 nop 186 187 /* CPWAIT sequence to make sure the MMU is on... */ 188 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 189 mov r2, r2 /* force it to complete */ 190 mov pc, r0 /* leap to kernel entry point! */ 191 192.Lbrh_becc_vbase: 193 .word ((BRH_BECC_VBASE >> L1_S_SHIFT) * 4) 194 195.Lbrh_uart1_vbase: 196 .word ((BRH_UART1_VBASE >> L1_S_SHIFT) * 4) 197 198.Lbrh_uart2_vbase: 199 .word ((BRH_UART2_VBASE >> L1_S_SHIFT) * 4) 200 201.Lbrh_led_vbase: 202 .word ((BRH_LED_VBASE >> L1_S_SHIFT) * 4) 203 204.Ltable: 205 .word 0xc0004000 206 207.Lstart: 208 .word start 209