xref: /netbsd-src/sys/arch/cobalt/dev/gt.c (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0)
1 /*	$NetBSD: gt.c,v 1.22 2009/11/27 03:23:05 rmind Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.22 2009/11/27 03:23:05 rmind Exp $");
30 
31 #include "opt_pci.h"
32 #include "pci.h"
33 
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/ioctl.h>
37 #include <sys/select.h>
38 #include <sys/tty.h>
39 #include <sys/proc.h>
40 #include <sys/conf.h>
41 #include <sys/file.h>
42 #include <sys/uio.h>
43 #include <sys/kernel.h>
44 #include <sys/syslog.h>
45 #include <sys/types.h>
46 #include <sys/device.h>
47 #include <sys/malloc.h>
48 #include <sys/extent.h>
49 
50 #include <machine/autoconf.h>
51 #include <machine/bus.h>
52 #include <machine/intr.h>
53 
54 #include <mips/cache.h>
55 
56 #include <dev/pci/pcivar.h>
57 #ifdef PCI_NETBSD_CONFIGURE
58 #include <dev/pci/pciconf.h>
59 #endif
60 
61 #include <cobalt/dev/gtreg.h>
62 
63 struct gt_softc {
64 	device_t	sc_dev;
65 
66 	bus_space_tag_t sc_bst;
67 	bus_space_handle_t sc_bsh;
68 	struct cobalt_pci_chipset sc_pc;
69 };
70 
71 static int	gt_match(device_t, cfdata_t, void *);
72 static void	gt_attach(device_t, device_t, void *);
73 static int	gt_print(void *aux, const char *pnp);
74 
75 static void	gt_timer_init(struct gt_softc *sc);
76 #if 0 /* unused */
77 static void	gt_timer0_init(void *);
78 static long	gt_timer0_read(void *);
79 #endif
80 
81 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc),
82     gt_match, gt_attach, NULL, NULL);
83 
84 static int
85 gt_match(device_t parent, cfdata_t cf, void *aux)
86 {
87 
88 	return 1;
89 }
90 
91 #define GT_REG_REGION	0x1000
92 
93 static void
94 gt_attach(device_t parent, device_t self, void *aux)
95 {
96 	struct gt_softc *sc = device_private(self);
97 	struct mainbus_attach_args *ma = aux;
98 #if NPCI > 0
99 	pci_chipset_tag_t pc;
100 	struct pcibus_attach_args pba;
101 #endif
102 
103 	sc->sc_dev = self;
104 	sc->sc_bst = ma->ma_iot;
105 	if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION,
106 	    0, &sc->sc_bsh)) {
107 		aprint_error(": unable to map GT64111 registers\n");
108 		return;
109 	}
110 
111 	aprint_normal("\n");
112 
113 	gt_timer_init(sc);
114 
115 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND,
116 	    (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) &
117 	    ~PCI_SYNCMODE) | PCI_PCLK_HIGH);
118 
119 	(void)bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY);
120 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY,
121 	    0x00 << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff);
122 
123 #if NPCI > 0
124 	pc = &sc->sc_pc;
125 	pc->pc_bst = sc->sc_bst;
126 	pc->pc_bsh = sc->sc_bsh;
127 
128 #ifdef PCI_NETBSD_CONFIGURE
129 	pc->pc_ioext = extent_create("pciio", 0x10001000, 0x11ffffff,
130 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
131 	pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff,
132 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
133 	pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
134 	    mips_dcache_align);
135 #endif
136 	pba.pba_dmat = &pci_bus_dma_tag;
137 	pba.pba_dmat64 = NULL;
138 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
139 	pba.pba_bus = 0;
140 	pba.pba_bridgetag = NULL;
141 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
142 		PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY;
143 	pba.pba_pc = pc;
144 	config_found_ia(self, "pcibus", &pba, gt_print);
145 #endif
146 }
147 
148 static int
149 gt_print(void *aux, const char *pnp)
150 {
151 
152 	/* XXX */
153 	return 0;
154 }
155 
156 static void
157 gt_timer_init(struct gt_softc *sc)
158 {
159 
160 	/* stop timer0 */
161 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
162 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0);
163 	/* mask timer0 interrupt */
164 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK,
165 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) & ~T0EXP);
166 }
167 
168 #if 0	/* unused; now NetBSD/cobalt uses CPU INT5 for hardclock(9) */
169 #define TIMER0_INIT_VALUE 500000
170 
171 static void
172 gt_timer0_init(void *cookie)
173 {
174 	struct gt_softc *sc = cookie;
175 
176 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
177 	    GT_TIMER_COUNTER0, TIMER0_INIT_VALUE);
178 	/* start timer0 */
179 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
180 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0);
181 	/* unmask timer0 interrupt */
182 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK,
183 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) | T0EXP);
184 }
185 
186 static long
187 gt_timer0_read(void *cookie)
188 {
189 	struct gt_softc *sc = cookie;
190 	uint32_t counter0;
191 
192 	counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0);
193 	counter0 = TIMER0_INIT_VALUE - counter0;
194 #if 0
195 	counter /= 50;
196 #else
197 	/*
198 	 * From pmax/pmax/dec_3min.c:
199 	 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512...
200 	 */
201 	counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11);
202 #endif
203 	return counter0;
204 }
205 #endif
206