xref: /netbsd-src/sys/arch/cobalt/dev/gt.c (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /*	$NetBSD: gt.c,v 1.12 2004/08/30 15:05:16 drochner Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.12 2004/08/30 15:05:16 drochner Exp $");
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/ioctl.h>
34 #include <sys/select.h>
35 #include <sys/tty.h>
36 #include <sys/proc.h>
37 #include <sys/user.h>
38 #include <sys/conf.h>
39 #include <sys/file.h>
40 #include <sys/uio.h>
41 #include <sys/kernel.h>
42 #include <sys/syslog.h>
43 #include <sys/types.h>
44 #include <sys/device.h>
45 
46 #include <machine/autoconf.h>
47 #include <machine/bus.h>
48 #include <machine/intr.h>
49 
50 #include <dev/pci/pcivar.h>
51 
52 #include <cobalt/cobalt/clockvar.h>
53 #include <cobalt/dev/gtreg.h>
54 
55 #include "pci.h"
56 
57 struct gt_softc {
58 	struct device	sc_dev;
59 
60 	bus_space_tag_t sc_bst;
61 	bus_space_handle_t sc_bsh;
62 	struct cobalt_pci_chipset sc_pc;
63 };
64 
65 static int	gt_match(struct device *, struct cfdata *, void *);
66 static void	gt_attach(struct device *, struct device *, void *);
67 static int	gt_print(void *aux, const char *pnp);
68 
69 static void	gt_timer_init(struct gt_softc *sc);
70 static void	gt_timer0_init(void *);
71 static long	gt_timer0_read(void *);
72 
73 CFATTACH_DECL(gt, sizeof(struct gt_softc),
74     gt_match, gt_attach, NULL, NULL);
75 
76 static int
77 gt_match(parent, match, aux)
78 	struct device *parent;
79 	struct cfdata *match;
80 	void *aux;
81 {
82 	return 1;
83 }
84 
85 #define GT_REG_REGION	0x1000
86 
87 static void
88 gt_attach(parent, self, aux)
89 	struct device *parent;
90 	struct device *self;
91 	void *aux;
92 {
93 	struct mainbus_attach_args *ma = aux;
94 	struct gt_softc *sc = (void *)self;
95 #if NPCI > 0
96 	pci_chipset_tag_t pc;
97 	struct pcibus_attach_args pba;
98 #endif
99 
100 	sc->sc_bst = ma->ma_iot;
101 	if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION,
102 	    0, &sc->sc_bsh)) {
103 		printf(": unable to map GT64111 registers\n");
104 		return;
105 	}
106 
107 	printf("\n");
108 
109 	gt_timer_init(sc);
110 
111 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND,
112 	    (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) &
113 	    ~PCI_SYNCMODE) | PCI_PCLK_HIGH);
114 
115 #if NPCI > 0
116 	pc = &sc->sc_pc;
117 	pc->pc_bst = sc->sc_bst;
118 	pc->pc_bsh = sc->sc_bsh;
119 
120 	pba.pba_dmat = &pci_bus_dma_tag;
121 	pba.pba_dmat64 = NULL;
122 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
123 	pba.pba_bus = 0;
124 	pba.pba_bridgetag = NULL;
125 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
126 		PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY;
127 	pba.pba_pc = pc;
128 	config_found_ia(self, "pcibus", &pba, gt_print);
129 #endif
130 }
131 
132 static int
133 gt_print(aux, pnp)
134 	void *aux;
135 	const char *pnp;
136 {
137 	/* XXX */
138 	return 0;
139 }
140 
141 static void
142 gt_timer_init(struct gt_softc *sc)
143 {
144 
145 	/* stop timer0 */
146 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
147 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0);
148 
149 	timer_start = gt_timer0_init;
150 	timer_read  = gt_timer0_read;
151 	timer_cookie = sc;
152 }
153 
154 #define TIMER0_INIT_VALUE 500000
155 
156 static void
157 gt_timer0_init(void *cookie)
158 {
159 	struct gt_softc *sc = cookie;
160 
161 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
162 	    GT_TIMER_COUNTER0, TIMER0_INIT_VALUE);
163 	/* start timer0 */
164 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
165 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0);
166 }
167 
168 static long
169 gt_timer0_read(void *cookie)
170 {
171 	struct gt_softc *sc = cookie;
172 	uint32_t counter0;
173 
174 	counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0);
175 	counter0 = TIMER0_INIT_VALUE - counter0;
176 #if 0
177 	counter /= 50;
178 #else
179 	/*
180 	 * From pmax/pmax/dec_3min.c:
181 	 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512...
182 	 */
183 	counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11);
184 #endif
185 	return counter0;
186 }
187