1 /* $NetBSD: pci_machdep.c,v 1.56 2018/02/09 15:24:35 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.56 2018/02/09 15:24:35 tsutsui Exp $"); 36 37 #include "opt_mbtype.h" 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/time.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #define _ATARI_BUS_DMA_PRIVATE 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/cpu.h> 57 #include <machine/iomap.h> 58 #include <machine/mfp.h> 59 60 #include <atari/atari/device.h> 61 #include <atari/pci/pci_vga.h> 62 63 /* 64 * Sizes of pci memory and I/O area. 65 */ 66 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 67 #define PCI_IO_END 0x10000000 /* 256 MByte */ 68 69 /* 70 * We preserve some space at the begin of the pci area for 32BIT_1M 71 * devices and standard vga. 72 */ 73 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 74 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 75 I/O addresses up to 0xffff) */ 76 77 /* 78 * PCI memory and IO should be aligned acording to this masks 79 */ 80 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 81 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 82 83 /* 84 * Convert a PCI 'device' number to a slot number. 85 */ 86 #define DEV2SLOT(dev) (3 - dev) 87 88 /* 89 * Struct to hold the memory and I/O datas of the pci devices 90 */ 91 struct pci_memreg { 92 LIST_ENTRY(pci_memreg) link; 93 int dev; 94 pcitag_t tag; 95 pcireg_t reg, address, mask; 96 u_int32_t size; 97 u_int32_t csr; 98 }; 99 100 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 101 102 /* 103 * Entry points for PCI DMA. Use only the 'standard' functions. 104 */ 105 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 106 bus_size_t, int, bus_dmamap_t *); 107 struct atari_bus_dma_tag pci_bus_dma_tag = { 108 0, 109 #if defined(_ATARIHW_) 110 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 111 #else 112 0, 113 #endif 114 _bus_dmamap_create, 115 _bus_dmamap_destroy, 116 _bus_dmamap_load, 117 _bus_dmamap_load_mbuf, 118 _bus_dmamap_load_uio, 119 _bus_dmamap_load_raw, 120 _bus_dmamap_unload, 121 _bus_dmamap_sync, 122 }; 123 124 int ataripcibusprint(void *, const char *); 125 int pcibusmatch(device_t, cfdata_t, void *); 126 void pcibusattach(device_t, device_t, void *); 127 128 static void enable_pci_devices(void); 129 static void insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem); 130 static int overlap_pci_areas(struct pci_memreg *p, 131 struct pci_memreg *self, u_int addr, u_int size, u_int what); 132 133 CFATTACH_DECL_NEW(pcib, 0, 134 pcibusmatch, pcibusattach, NULL, NULL); 135 136 /* 137 * We need some static storage to probe pci-busses for VGA cards during 138 * early console init. 139 */ 140 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 141 142 int 143 pcibusmatch(device_t parent, cfdata_t cf, void *aux) 144 { 145 static int nmatched = 0; 146 147 if (strcmp((char *)aux, "pcib")) 148 return 0; /* Wrong number... */ 149 150 if (atari_realconfig == 0) 151 return 1; 152 153 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 154 /* 155 * Both Hades and Milan have only one pci bus 156 */ 157 if (nmatched) 158 return 0; 159 nmatched++; 160 return 1; 161 } 162 return 0; 163 } 164 165 void 166 pcibusattach(device_t parent, device_t self, void *aux) 167 { 168 struct pcibus_attach_args pba; 169 170 pba.pba_pc = NULL; 171 pba.pba_bus = 0; 172 pba.pba_bridgetag = NULL; 173 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 174 pba.pba_dmat = &pci_bus_dma_tag; 175 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 176 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 177 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 178 printf("leb_alloc_bus_space_tag failed!\n"); 179 return; 180 } 181 pba.pba_iot->base = PCI_IO_PHYS; 182 pba.pba_memt->base = PCI_MEM_PHYS; 183 184 if (self == NULL) { 185 /* 186 * Scan the bus for a VGA-card that we support. If we 187 * find one, try to initialize it to a 'standard' text 188 * mode (80x25). 189 */ 190 check_for_vga(pba.pba_iot, pba.pba_memt); 191 return; 192 } 193 194 enable_pci_devices(); 195 196 #if defined(_ATARIHW_) 197 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 198 #endif 199 200 printf("\n"); 201 202 config_found_ia(self, "pcibus", &pba, ataripcibusprint); 203 } 204 205 int 206 ataripcibusprint(void *aux, const char *name) 207 { 208 209 if (name == NULL) 210 return UNCONF; 211 return QUIET; 212 } 213 214 void 215 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 216 { 217 } 218 219 /* 220 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 221 * We only disable all devices here. Memory and I/O enabling is done 222 * later at pcibusattach. 223 */ 224 void 225 init_pci_bus(void) 226 { 227 pci_chipset_tag_t pc = NULL; /* XXX */ 228 pcitag_t tag; 229 pcireg_t csr; 230 int device, id, maxndevs; 231 232 tag = 0; 233 id = 0; 234 235 maxndevs = pci_bus_maxdevs(pc, 0); 236 237 for (device = 0; device < maxndevs; device++) { 238 239 tag = pci_make_tag(pc, 0, device, 0); 240 id = pci_conf_read(pc, tag, PCI_ID_REG); 241 if (id == 0 || id == 0xffffffff) 242 continue; 243 244 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 245 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 246 csr &= ~PCI_COMMAND_MASTER_ENABLE; 247 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 248 } 249 } 250 251 /* 252 * insert a new element in an existing list that the ID's (size in struct 253 * pci_memreg) are sorted. 254 */ 255 static void 256 insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem) 257 { 258 struct pci_memreg *p, *q; 259 260 p = LIST_FIRST(head); 261 q = NULL; 262 263 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 264 265 if (q == NULL) { 266 LIST_INSERT_HEAD(head, elem, link); 267 } else { 268 LIST_INSERT_AFTER(q, elem, link); 269 } 270 } 271 272 /* 273 * Test if a new selected area overlaps with an already (probably preselected) 274 * pci area. 275 */ 276 static int 277 overlap_pci_areas(struct pci_memreg *p, struct pci_memreg *self, u_int addr, u_int size, u_int what) 278 { 279 struct pci_memreg *q; 280 281 if (p == NULL) 282 return 0; 283 284 q = p; 285 while (q != NULL) { 286 if ((q != self) && (q->csr & what)) { 287 if ((addr >= q->address) && (addr < (q->address + q->size))) { 288 #ifdef DEBUG_PCI_MACHDEP 289 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 290 self->dev, self->reg, q->dev, q->reg); 291 #endif 292 return 1; 293 } 294 if ((q->address >= addr) && (q->address < (addr + size))) { 295 #ifdef DEBUG_PCI_MACHDEP 296 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 297 self->dev, self->reg, q->dev, q->reg); 298 #endif 299 return 1; 300 } 301 } 302 q = LIST_NEXT(q, link); 303 } 304 return 0; 305 } 306 307 /* 308 * Enable memory and I/O on pci devices. Care about already enabled devices 309 * (probabaly by the console driver). 310 * 311 * The idea behind the following code is: 312 * We build a by sizes sorted list of the requirements of the different 313 * pci devices. After that we choose the start addresses of that areas 314 * in such a way that they are placed as closed as possible together. 315 */ 316 static void 317 enable_pci_devices(void) 318 { 319 PCI_MEMREG memlist; 320 PCI_MEMREG iolist; 321 struct pci_memreg *p, *q; 322 int dev, reg, id, class; 323 pcitag_t tag; 324 pcireg_t csr, address, mask; 325 pci_chipset_tag_t pc; 326 int sizecnt, membase_1m; 327 328 pc = 0; 329 csr = 0; 330 tag = 0; 331 332 LIST_INIT(&memlist); 333 LIST_INIT(&iolist); 334 335 /* 336 * first step: go through all devices and gather memory and I/O 337 * sizes 338 */ 339 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 340 341 tag = pci_make_tag(pc, 0, dev, 0); 342 id = pci_conf_read(pc, tag, PCI_ID_REG); 343 if (id == 0 || id == 0xffffffff) 344 continue; 345 346 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 347 348 /* 349 * special case: if a display card is found and memory is enabled 350 * preserve 128k at 0xa0000 as vga memory. 351 * XXX: if a display card is found without being enabled, leave 352 * it alone! You will usually only create conflicts by enabeling 353 * it. 354 */ 355 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 356 switch (PCI_CLASS(class)) { 357 case PCI_CLASS_PREHISTORIC: 358 case PCI_CLASS_DISPLAY: 359 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 360 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 361 M_TEMP, M_WAITOK); 362 memset(p, '\0', sizeof(struct pci_memreg)); 363 p->dev = dev; 364 p->csr = csr; 365 p->tag = tag; 366 p->reg = 0; /* there is no register about this */ 367 p->size = 0x20000; /* 128kByte */ 368 p->mask = 0xfffe0000; 369 p->address = 0xa0000; 370 371 insert_into_list(&memlist, p); 372 } 373 else continue; 374 } 375 376 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 377 378 address = pci_conf_read(pc, tag, reg); 379 pci_conf_write(pc, tag, reg, 0xffffffff); 380 mask = pci_conf_read(pc, tag, reg); 381 pci_conf_write(pc, tag, reg, address); 382 if (mask == 0) 383 continue; /* Register unused */ 384 385 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 386 M_TEMP, M_WAITOK); 387 memset(p, '\0', sizeof(struct pci_memreg)); 388 p->dev = dev; 389 p->csr = csr; 390 p->tag = tag; 391 p->reg = reg; 392 p->mask = mask; 393 p->address = 0; 394 395 if (mask & PCI_MAPREG_TYPE_IO) { 396 p->size = PCI_MAPREG_IO_SIZE(mask); 397 398 /* 399 * Align IO if necessary 400 */ 401 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 402 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 403 p->size = PCI_MAPREG_IO_SIZE(p->mask); 404 } 405 406 /* 407 * if I/O is already enabled (probably by the console driver) 408 * save the address in order to take care about it later. 409 */ 410 if (csr & PCI_COMMAND_IO_ENABLE) 411 p->address = address; 412 413 insert_into_list(&iolist, p); 414 } else { 415 p->size = PCI_MAPREG_MEM_SIZE(mask); 416 417 /* 418 * Align memory if necessary 419 */ 420 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 421 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 422 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 423 } 424 425 /* 426 * if memory is already enabled (probably by the console driver) 427 * save the address in order to take care about it later. 428 */ 429 if (csr & PCI_COMMAND_MEM_ENABLE) 430 p->address = address; 431 432 insert_into_list(&memlist, p); 433 434 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 435 reg++; 436 } 437 } 438 439 440 #if defined(_ATARIHW_) 441 /* 442 * Both interrupt pin & line are set to the device (== slot) 443 * number. This makes sense on the atari Hades because the 444 * individual slots are hard-wired to a specific MFP-pin. 445 */ 446 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 447 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 448 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 449 #else 450 /* 451 * On the Milan, we accept the BIOS's choice. 452 */ 453 /* ..except the secondary IDE interrupt that the BIOS doesn't setup. */ 454 #define PIIX_PCIB_MBIRQ0 0x70 455 if ((PCI_VENDOR(id) == PCI_VENDOR_INTEL) && 456 (PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_82371FB_ISA)) { 457 /* 458 * Set Interrupt Routing for MBIRQ0 to IRQ15. 459 * Note Milan's ROM bootloader v1.2 and v1.4 incorrectly 460 * set MBIRQ0 to IRQ14 (not 15) and unused MBIRQ1 to IRQ 15, 461 * so explicitly disable MBIRQ1. 462 */ 463 csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0); 464 csr &= ~0x000ffff; 465 csr |= 0x000800f; /* MBIRQ1: disable, MBIRQ0: IRQ15 */ 466 pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr); 467 #ifdef DEBUG_PCI_MACHDEP 468 printf("\npcib0: enable and route MBIRQ0 to irq 15\n"); 469 #endif 470 } 471 #endif 472 } 473 474 /* 475 * second step: calculate the memory and I/O addresses beginning from 476 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 477 * 478 * begin with memory list 479 */ 480 481 address = PCI_MEM_START; 482 sizecnt = 0; 483 membase_1m = 0; 484 p = LIST_FIRST(&memlist); 485 while (p != NULL) { 486 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 487 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 488 if (p->size > membase_1m) 489 membase_1m = p->size; 490 do { 491 p->address = membase_1m; 492 membase_1m += p->size; 493 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 494 p->size, PCI_COMMAND_MEM_ENABLE)); 495 if (membase_1m > 0x00100000) { 496 /* 497 * Should we panic here? 498 */ 499 printf("\npcibus0: dev %d reg %d: memory not configured", 500 p->dev, p->reg); 501 p->reg = 0; 502 } 503 } else { 504 505 if (sizecnt && (p->size > sizecnt)) 506 sizecnt = ((p->size + sizecnt) & p->mask) & 507 PCI_MAPREG_MEM_ADDR_MASK; 508 if (sizecnt > address) { 509 address = sizecnt; 510 sizecnt = 0; 511 } 512 513 do { 514 p->address = address + sizecnt; 515 sizecnt += p->size; 516 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 517 p->size, PCI_COMMAND_MEM_ENABLE)); 518 519 if ((address + sizecnt) > PCI_MEM_END) { 520 /* 521 * Should we panic here? 522 */ 523 printf("\npcibus0: dev %d reg %d: memory not configured", 524 p->dev, p->reg); 525 p->reg = 0; 526 } 527 } 528 if (p->reg > 0) { 529 pci_conf_write(pc, p->tag, p->reg, p->address); 530 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 531 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 532 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 533 p->csr = csr; 534 } 535 } 536 p = LIST_NEXT(p, link); 537 } 538 539 /* 540 * now the I/O list 541 */ 542 543 address = PCI_IO_START; 544 sizecnt = 0; 545 p = LIST_FIRST(&iolist); 546 while (p != NULL) { 547 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 548 549 if (sizecnt && (p->size > sizecnt)) 550 sizecnt = ((p->size + sizecnt) & p->mask) & 551 PCI_MAPREG_IO_ADDR_MASK; 552 if (sizecnt > address) { 553 address = sizecnt; 554 sizecnt = 0; 555 } 556 557 do { 558 p->address = address + sizecnt; 559 sizecnt += p->size; 560 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 561 p->size, PCI_COMMAND_IO_ENABLE)); 562 563 if ((address + sizecnt) > PCI_IO_END) { 564 /* 565 * Should we panic here? 566 */ 567 printf("\npcibus0: dev %d reg %d: io not configured", 568 p->dev, p->reg); 569 } else { 570 pci_conf_write(pc, p->tag, p->reg, p->address); 571 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 572 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 573 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 574 p->csr = csr; 575 } 576 } 577 p = LIST_NEXT(p, link); 578 } 579 580 #ifdef DEBUG_PCI_MACHDEP 581 printf("\nI/O List:\n"); 582 p = LIST_FIRST(&iolist); 583 584 while (p != NULL) { 585 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 586 p->reg, p->size, p->address); 587 p = LIST_NEXT(p, link); 588 } 589 printf("\nMemlist:"); 590 p = LIST_FIRST(&memlist); 591 592 while (p != NULL) { 593 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 594 p->reg, p->size, p->address); 595 p = LIST_NEXT(p, link); 596 } 597 #endif 598 599 /* 600 * Free the lists 601 */ 602 p = LIST_FIRST(&iolist); 603 while (p != NULL) { 604 q = p; 605 LIST_REMOVE(q, link); 606 free(p, M_WAITOK); 607 p = LIST_FIRST(&iolist); 608 } 609 p = LIST_FIRST(&memlist); 610 while (p != NULL) { 611 q = p; 612 LIST_REMOVE(q, link); 613 free(p, M_WAITOK); 614 p = LIST_FIRST(&memlist); 615 } 616 } 617 618 pcitag_t 619 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 620 { 621 622 return (bus << 16) | (device << 11) | (function << 8); 623 } 624 625 void 626 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 627 { 628 629 if (bp != NULL) 630 *bp = (tag >> 16) & 0xff; 631 if (dp != NULL) 632 *dp = (tag >> 11) & 0x1f; 633 if (fp != NULL) 634 *fp = (tag >> 8) & 0x7; 635 } 636 637 int 638 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 639 { 640 int line = pa->pa_intrline; 641 642 #if defined(_MILANHW_) 643 /* 644 * On the Hades, the 'pin' info is useless. 645 */ 646 { 647 int pin = pa->pa_intrpin; 648 649 if (pin == 0) { 650 /* No IRQ used. */ 651 goto bad; 652 } 653 if (pin > PCI_INTERRUPT_PIN_MAX) { 654 printf("pci_intr_map: bad interrupt pin %d\n", pin); 655 goto bad; 656 } 657 } 658 #endif /* _MILANHW_ */ 659 660 /* 661 * According to the PCI-spec, 255 means `unknown' or `no connection'. 662 * Interpret this as 'no interrupt assigned'. 663 */ 664 if (line == 255) 665 goto bad; 666 667 /* 668 * Values are pretty useless on the Hades since all interrupt 669 * lines for a card are tied together and hardwired to a 670 * specific TT-MFP I/O port. 671 * On the Milan, they are tied to the ICU. 672 */ 673 #if defined(_MILANHW_) 674 if (line >= 16) { 675 printf("pci_intr_map: bad interrupt line %d\n", line); 676 goto bad; 677 } 678 if (line == 2) { 679 printf("pci_intr_map: changed line 2 to line 9\n"); 680 line = 9; 681 } 682 /* Assume line == 0 means unassigned */ 683 if (line == 0) 684 goto bad; 685 #endif 686 *ihp = line; 687 return 0; 688 689 bad: 690 *ihp = -1; 691 return 1; 692 } 693 694 const char * 695 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, size_t len) 696 { 697 if (ih == -1) 698 panic("pci_intr_string: bogus handle 0x%x", ih); 699 700 snprintf(buf, len, "irq %d", ih); 701 return buf; 702 703 } 704 705 const struct evcnt * 706 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 707 { 708 709 /* XXX for now, no evcnt parent reported */ 710 return NULL; 711 } 712