1 /* $NetBSD: pci_machdep.c,v 1.48 2010/04/13 11:31:11 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.48 2010/04/13 11:31:11 tsutsui Exp $"); 36 37 #include "opt_mbtype.h" 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/time.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #define _ATARI_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <machine/cpu.h> 56 #include <machine/iomap.h> 57 #include <machine/mfp.h> 58 59 #include <atari/atari/device.h> 60 #include <atari/pci/pci_vga.h> 61 62 /* 63 * Sizes of pci memory and I/O area. 64 */ 65 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 66 #define PCI_IO_END 0x10000000 /* 256 MByte */ 67 68 /* 69 * We preserve some space at the begin of the pci area for 32BIT_1M 70 * devices and standard vga. 71 */ 72 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 73 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 74 I/O addresses up to 0xffff) */ 75 76 /* 77 * PCI memory and IO should be aligned acording to this masks 78 */ 79 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 80 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 81 82 /* 83 * Convert a PCI 'device' number to a slot number. 84 */ 85 #define DEV2SLOT(dev) (3 - dev) 86 87 /* 88 * Struct to hold the memory and I/O datas of the pci devices 89 */ 90 struct pci_memreg { 91 LIST_ENTRY(pci_memreg) link; 92 int dev; 93 pcitag_t tag; 94 pcireg_t reg, address, mask; 95 u_int32_t size; 96 u_int32_t csr; 97 }; 98 99 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 100 101 /* 102 * Entry points for PCI DMA. Use only the 'standard' functions. 103 */ 104 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 105 bus_size_t, int, bus_dmamap_t *); 106 struct atari_bus_dma_tag pci_bus_dma_tag = { 107 0, 108 #if defined(_ATARIHW_) 109 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 110 #else 111 0, 112 #endif 113 _bus_dmamap_create, 114 _bus_dmamap_destroy, 115 _bus_dmamap_load, 116 _bus_dmamap_load_mbuf, 117 _bus_dmamap_load_uio, 118 _bus_dmamap_load_raw, 119 _bus_dmamap_unload, 120 _bus_dmamap_sync, 121 }; 122 123 int ataripcibusprint(void *auxp, const char *); 124 int pcibusmatch(struct device *, struct cfdata *, void *); 125 void pcibusattach(struct device *, struct device *, void *); 126 127 static void enable_pci_devices(void); 128 static void insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem); 129 static int overlap_pci_areas(struct pci_memreg *p, 130 struct pci_memreg *self, u_int addr, u_int size, u_int what); 131 132 CFATTACH_DECL(pcib, sizeof(struct device), 133 pcibusmatch, pcibusattach, NULL, NULL); 134 135 /* 136 * We need some static storage to probe pci-busses for VGA cards during 137 * early console init. 138 */ 139 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 140 141 int 142 pcibusmatch(struct device *pdp, struct cfdata *cfp, void *auxp) 143 { 144 static int nmatched = 0; 145 146 if (strcmp((char *)auxp, "pcib")) 147 return 0; /* Wrong number... */ 148 149 if (atari_realconfig == 0) 150 return 1; 151 152 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 153 /* 154 * Both Hades and Milan have only one pci bus 155 */ 156 if (nmatched) 157 return 0; 158 nmatched++; 159 return 1; 160 } 161 return 0; 162 } 163 164 void 165 pcibusattach(struct device *pdp, struct device *dp, void *auxp) 166 { 167 struct pcibus_attach_args pba; 168 169 pba.pba_pc = NULL; 170 pba.pba_bus = 0; 171 pba.pba_bridgetag = NULL; 172 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 173 pba.pba_dmat = &pci_bus_dma_tag; 174 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 175 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 176 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 177 printf("leb_alloc_bus_space_tag failed!\n"); 178 return; 179 } 180 pba.pba_iot->base = PCI_IO_PHYS; 181 pba.pba_memt->base = PCI_MEM_PHYS; 182 183 if (dp == NULL) { 184 /* 185 * Scan the bus for a VGA-card that we support. If we 186 * find one, try to initialize it to a 'standard' text 187 * mode (80x25). 188 */ 189 check_for_vga(pba.pba_iot, pba.pba_memt); 190 return; 191 } 192 193 enable_pci_devices(); 194 195 #if defined(_ATARIHW_) 196 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 197 #endif 198 199 printf("\n"); 200 201 config_found_ia(dp, "pcibus", &pba, ataripcibusprint); 202 } 203 204 int 205 ataripcibusprint(void *auxp, const char *name) 206 { 207 208 if (name == NULL) 209 return UNCONF; 210 return QUIET; 211 } 212 213 void 214 pci_attach_hook(struct device *parent, struct device *self, struct pcibus_attach_args *pba) 215 { 216 } 217 218 /* 219 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 220 * We only disable all devices here. Memory and I/O enabling is done 221 * later at pcibusattach. 222 */ 223 void 224 init_pci_bus(void) 225 { 226 pci_chipset_tag_t pc = NULL; /* XXX */ 227 pcitag_t tag; 228 pcireg_t csr; 229 int device, id, maxndevs; 230 231 tag = 0; 232 id = 0; 233 234 maxndevs = pci_bus_maxdevs(pc, 0); 235 236 for (device = 0; device < maxndevs; device++) { 237 238 tag = pci_make_tag(pc, 0, device, 0); 239 id = pci_conf_read(pc, tag, PCI_ID_REG); 240 if (id == 0 || id == 0xffffffff) 241 continue; 242 243 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 244 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 245 csr &= ~PCI_COMMAND_MASTER_ENABLE; 246 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 247 } 248 } 249 250 /* 251 * insert a new element in an existing list that the ID's (size in struct 252 * pci_memreg) are sorted. 253 */ 254 static void 255 insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem) 256 { 257 struct pci_memreg *p, *q; 258 259 p = LIST_FIRST(head); 260 q = NULL; 261 262 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 263 264 if (q == NULL) { 265 LIST_INSERT_HEAD(head, elem, link); 266 } else { 267 LIST_INSERT_AFTER(q, elem, link); 268 } 269 } 270 271 /* 272 * Test if a new selected area overlaps with an already (probably preselected) 273 * pci area. 274 */ 275 static int 276 overlap_pci_areas(struct pci_memreg *p, struct pci_memreg *self, u_int addr, u_int size, u_int what) 277 { 278 struct pci_memreg *q; 279 280 if (p == NULL) 281 return 0; 282 283 q = p; 284 while (q != NULL) { 285 if ((q != self) && (q->csr & what)) { 286 if ((addr >= q->address) && (addr < (q->address + q->size))) { 287 #ifdef DEBUG_PCI_MACHDEP 288 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 289 self->dev, self->reg, q->dev, q->reg); 290 #endif 291 return 1; 292 } 293 if ((q->address >= addr) && (q->address < (addr + size))) { 294 #ifdef DEBUG_PCI_MACHDEP 295 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 296 self->dev, self->reg, q->dev, q->reg); 297 #endif 298 return 1; 299 } 300 } 301 q = LIST_NEXT(q, link); 302 } 303 return 0; 304 } 305 306 /* 307 * Enable memory and I/O on pci devices. Care about already enabled devices 308 * (probabaly by the console driver). 309 * 310 * The idea behind the following code is: 311 * We build a by sizes sorted list of the requirements of the different 312 * pci devices. After that we choose the start addresses of that areas 313 * in such a way that they are placed as closed as possible together. 314 */ 315 static void 316 enable_pci_devices(void) 317 { 318 PCI_MEMREG memlist; 319 PCI_MEMREG iolist; 320 struct pci_memreg *p, *q; 321 int dev, reg, id, class; 322 pcitag_t tag; 323 pcireg_t csr, address, mask; 324 pci_chipset_tag_t pc; 325 int sizecnt, membase_1m; 326 327 pc = 0; 328 csr = 0; 329 tag = 0; 330 331 LIST_INIT(&memlist); 332 LIST_INIT(&iolist); 333 334 /* 335 * first step: go through all devices and gather memory and I/O 336 * sizes 337 */ 338 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 339 340 tag = pci_make_tag(pc, 0, dev, 0); 341 id = pci_conf_read(pc, tag, PCI_ID_REG); 342 if (id == 0 || id == 0xffffffff) 343 continue; 344 345 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 346 347 /* 348 * special case: if a display card is found and memory is enabled 349 * preserve 128k at 0xa0000 as vga memory. 350 * XXX: if a display card is found without being enabled, leave 351 * it alone! You will usually only create conflicts by enabeling 352 * it. 353 */ 354 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 355 switch (PCI_CLASS(class)) { 356 case PCI_CLASS_PREHISTORIC: 357 case PCI_CLASS_DISPLAY: 358 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 359 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 360 M_TEMP, M_WAITOK); 361 memset(p, '\0', sizeof(struct pci_memreg)); 362 p->dev = dev; 363 p->csr = csr; 364 p->tag = tag; 365 p->reg = 0; /* there is no register about this */ 366 p->size = 0x20000; /* 128kByte */ 367 p->mask = 0xfffe0000; 368 p->address = 0xa0000; 369 370 insert_into_list(&memlist, p); 371 } 372 else continue; 373 } 374 375 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 376 377 address = pci_conf_read(pc, tag, reg); 378 pci_conf_write(pc, tag, reg, 0xffffffff); 379 mask = pci_conf_read(pc, tag, reg); 380 pci_conf_write(pc, tag, reg, address); 381 if (mask == 0) 382 continue; /* Register unused */ 383 384 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 385 M_TEMP, M_WAITOK); 386 memset(p, '\0', sizeof(struct pci_memreg)); 387 p->dev = dev; 388 p->csr = csr; 389 p->tag = tag; 390 p->reg = reg; 391 p->mask = mask; 392 p->address = 0; 393 394 if (mask & PCI_MAPREG_TYPE_IO) { 395 p->size = PCI_MAPREG_IO_SIZE(mask); 396 397 /* 398 * Align IO if necessary 399 */ 400 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 401 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 402 p->size = PCI_MAPREG_IO_SIZE(p->mask); 403 } 404 405 /* 406 * if I/O is already enabled (probably by the console driver) 407 * save the address in order to take care about it later. 408 */ 409 if (csr & PCI_COMMAND_IO_ENABLE) 410 p->address = address; 411 412 insert_into_list(&iolist, p); 413 } else { 414 p->size = PCI_MAPREG_MEM_SIZE(mask); 415 416 /* 417 * Align memory if necessary 418 */ 419 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 420 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 421 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 422 } 423 424 /* 425 * if memory is already enabled (probably by the console driver) 426 * save the address in order to take care about it later. 427 */ 428 if (csr & PCI_COMMAND_MEM_ENABLE) 429 p->address = address; 430 431 insert_into_list(&memlist, p); 432 433 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 434 reg++; 435 } 436 } 437 438 439 #if defined(_ATARIHW_) 440 /* 441 * Both interrupt pin & line are set to the device (== slot) 442 * number. This makes sense on the atari Hades because the 443 * individual slots are hard-wired to a specific MFP-pin. 444 */ 445 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 446 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 447 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 448 #else 449 /* 450 * On the Milan, we accept the BIOS's choice. 451 */ 452 #endif 453 } 454 455 /* 456 * second step: calculate the memory and I/O addresses beginning from 457 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 458 * 459 * begin with memory list 460 */ 461 462 address = PCI_MEM_START; 463 sizecnt = 0; 464 membase_1m = 0; 465 p = LIST_FIRST(&memlist); 466 while (p != NULL) { 467 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 468 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 469 if (p->size > membase_1m) 470 membase_1m = p->size; 471 do { 472 p->address = membase_1m; 473 membase_1m += p->size; 474 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 475 p->size, PCI_COMMAND_MEM_ENABLE)); 476 if (membase_1m > 0x00100000) { 477 /* 478 * Should we panic here? 479 */ 480 printf("\npcibus0: dev %d reg %d: memory not configured", 481 p->dev, p->reg); 482 p->reg = 0; 483 } 484 } else { 485 486 if (sizecnt && (p->size > sizecnt)) 487 sizecnt = ((p->size + sizecnt) & p->mask) & 488 PCI_MAPREG_MEM_ADDR_MASK; 489 if (sizecnt > address) { 490 address = sizecnt; 491 sizecnt = 0; 492 } 493 494 do { 495 p->address = address + sizecnt; 496 sizecnt += p->size; 497 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 498 p->size, PCI_COMMAND_MEM_ENABLE)); 499 500 if ((address + sizecnt) > PCI_MEM_END) { 501 /* 502 * Should we panic here? 503 */ 504 printf("\npcibus0: dev %d reg %d: memory not configured", 505 p->dev, p->reg); 506 p->reg = 0; 507 } 508 } 509 if (p->reg > 0) { 510 pci_conf_write(pc, p->tag, p->reg, p->address); 511 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 512 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 513 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 514 p->csr = csr; 515 } 516 } 517 p = LIST_NEXT(p, link); 518 } 519 520 /* 521 * now the I/O list 522 */ 523 524 address = PCI_IO_START; 525 sizecnt = 0; 526 p = LIST_FIRST(&iolist); 527 while (p != NULL) { 528 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 529 530 if (sizecnt && (p->size > sizecnt)) 531 sizecnt = ((p->size + sizecnt) & p->mask) & 532 PCI_MAPREG_IO_ADDR_MASK; 533 if (sizecnt > address) { 534 address = sizecnt; 535 sizecnt = 0; 536 } 537 538 do { 539 p->address = address + sizecnt; 540 sizecnt += p->size; 541 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 542 p->size, PCI_COMMAND_IO_ENABLE)); 543 544 if ((address + sizecnt) > PCI_IO_END) { 545 /* 546 * Should we panic here? 547 */ 548 printf("\npcibus0: dev %d reg %d: io not configured", 549 p->dev, p->reg); 550 } else { 551 pci_conf_write(pc, p->tag, p->reg, p->address); 552 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 553 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 554 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 555 p->csr = csr; 556 } 557 } 558 p = LIST_NEXT(p, link); 559 } 560 561 #ifdef DEBUG_PCI_MACHDEP 562 printf("\nI/O List:\n"); 563 p = LIST_FIRST(&iolist); 564 565 while (p != NULL) { 566 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 567 p->reg, p->size, p->address); 568 p = LIST_NEXT(p, link); 569 } 570 printf("\nMemlist:"); 571 p = LIST_FIRST(&memlist); 572 573 while (p != NULL) { 574 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 575 p->reg, p->size, p->address); 576 p = LIST_NEXT(p, link); 577 } 578 #endif 579 580 /* 581 * Free the lists 582 */ 583 p = LIST_FIRST(&iolist); 584 while (p != NULL) { 585 q = p; 586 LIST_REMOVE(q, link); 587 free(p, M_WAITOK); 588 p = LIST_FIRST(&iolist); 589 } 590 p = LIST_FIRST(&memlist); 591 while (p != NULL) { 592 q = p; 593 LIST_REMOVE(q, link); 594 free(p, M_WAITOK); 595 p = LIST_FIRST(&memlist); 596 } 597 } 598 599 pcitag_t 600 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 601 { 602 603 return (bus << 16) | (device << 11) | (function << 8); 604 } 605 606 void 607 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 608 { 609 610 if (bp != NULL) 611 *bp = (tag >> 16) & 0xff; 612 if (dp != NULL) 613 *dp = (tag >> 11) & 0x1f; 614 if (fp != NULL) 615 *fp = (tag >> 8) & 0x7; 616 } 617 618 int 619 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 620 { 621 int line = pa->pa_intrline; 622 623 #if defined(_MILANHW_) 624 /* 625 * On the Hades, the 'pin' info is useless. 626 */ 627 { 628 int pin = pa->pa_intrpin; 629 630 if (pin == 0) { 631 /* No IRQ used. */ 632 goto bad; 633 } 634 if (pin > PCI_INTERRUPT_PIN_MAX) { 635 printf("pci_intr_map: bad interrupt pin %d\n", pin); 636 goto bad; 637 } 638 } 639 #endif /* _MILANHW_ */ 640 641 /* 642 * According to the PCI-spec, 255 means `unknown' or `no connection'. 643 * Interpret this as 'no interrupt assigned'. 644 */ 645 if (line == 255) 646 goto bad; 647 648 /* 649 * Values are pretty useless on the Hades since all interrupt 650 * lines for a card are tied together and hardwired to a 651 * specific TT-MFP I/O port. 652 * On the Milan, they are tied to the ICU. 653 */ 654 #if defined(_MILANHW_) 655 if (line >= 16) { 656 printf("pci_intr_map: bad interrupt line %d\n", line); 657 goto bad; 658 } 659 if (line == 2) { 660 printf("pci_intr_map: changed line 2 to line 9\n"); 661 line = 9; 662 } 663 /* Assume line == 0 means unassigned */ 664 if (line == 0) 665 goto bad; 666 #endif 667 *ihp = line; 668 return 0; 669 670 bad: 671 *ihp = -1; 672 return 1; 673 } 674 675 const char * 676 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 677 { 678 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 679 680 if (ih == -1) 681 panic("pci_intr_string: bogus handle 0x%x", ih); 682 683 sprintf(irqstr, "irq %d", ih); 684 return irqstr; 685 686 } 687 688 const struct evcnt * 689 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 690 { 691 692 /* XXX for now, no evcnt parent reported */ 693 return NULL; 694 } 695