1 /* $NetBSD: pci_machdep.c,v 1.58 2019/05/04 08:30:06 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.58 2019/05/04 08:30:06 tsutsui Exp $"); 36 37 #include "opt_mbtype.h" 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/time.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #define _ATARI_BUS_DMA_PRIVATE 48 #include <sys/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/cpu.h> 57 #include <machine/iomap.h> 58 #include <machine/mfp.h> 59 60 #include <atari/atari/device.h> 61 #include <atari/pci/pci_vga.h> 62 63 /* 64 * Sizes of pci memory and I/O area. 65 */ 66 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 67 #define PCI_IO_END 0x10000000 /* 256 MByte */ 68 69 /* 70 * We preserve some space at the begin of the pci area for 32BIT_1M 71 * devices and standard vga. 72 */ 73 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 74 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 75 I/O addresses up to 0xffff) */ 76 77 /* 78 * PCI memory and IO should be aligned acording to this masks 79 */ 80 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 81 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 82 83 /* 84 * Convert a PCI 'device' number to a slot number. 85 */ 86 #define DEV2SLOT(dev) (3 - dev) 87 88 /* 89 * Struct to hold the memory and I/O datas of the pci devices 90 */ 91 struct pci_memreg { 92 LIST_ENTRY(pci_memreg) link; 93 int dev; 94 pcitag_t tag; 95 pcireg_t reg, address, mask; 96 uint32_t size; 97 uint32_t csr; 98 }; 99 100 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 101 102 /* 103 * Entry points for PCI DMA. Use only the 'standard' functions. 104 */ 105 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 106 bus_size_t, int, bus_dmamap_t *); 107 struct atari_bus_dma_tag pci_bus_dma_tag = { 108 0, 109 #if defined(_ATARIHW_) 110 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 111 #else 112 0, 113 #endif 114 _bus_dmamap_create, 115 _bus_dmamap_destroy, 116 _bus_dmamap_load, 117 _bus_dmamap_load_mbuf, 118 _bus_dmamap_load_uio, 119 _bus_dmamap_load_raw, 120 _bus_dmamap_unload, 121 _bus_dmamap_sync, 122 }; 123 124 int ataripcibusprint(void *, const char *); 125 int pcibusmatch(device_t, cfdata_t, void *); 126 void pcibusattach(device_t, device_t, void *); 127 128 static void enable_pci_devices(void); 129 static void insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem); 130 static int overlap_pci_areas(struct pci_memreg *p, 131 struct pci_memreg *self, u_int addr, u_int size, u_int what); 132 133 CFATTACH_DECL_NEW(pcib, 0, 134 pcibusmatch, pcibusattach, NULL, NULL); 135 136 /* 137 * We need some static storage to probe pci-busses for VGA cards during 138 * early console init. 139 */ 140 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 141 142 int 143 pcibusmatch(device_t parent, cfdata_t cf, void *aux) 144 { 145 static int nmatched = 0; 146 147 if (strcmp((char *)aux, "pcib")) 148 return 0; /* Wrong number... */ 149 150 if (atari_realconfig == 0) 151 return 1; 152 153 if ((machineid & (ATARI_HADES|ATARI_MILAN)) != 0) { 154 /* 155 * Both Hades and Milan have only one pci bus 156 */ 157 if (nmatched) 158 return 0; 159 nmatched++; 160 return 1; 161 } 162 return 0; 163 } 164 165 void 166 pcibusattach(device_t parent, device_t self, void *aux) 167 { 168 struct pcibus_attach_args pba; 169 170 pba.pba_pc = NULL; 171 pba.pba_bus = 0; 172 pba.pba_bridgetag = NULL; 173 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 174 pba.pba_dmat = &pci_bus_dma_tag; 175 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 176 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 177 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 178 printf("leb_alloc_bus_space_tag failed!\n"); 179 return; 180 } 181 pba.pba_iot->base = PCI_IO_PHYS; 182 pba.pba_memt->base = PCI_MEM_PHYS; 183 184 if (self == NULL) { 185 /* 186 * Scan the bus for a VGA-card that we support. If we 187 * find one, try to initialize it to a 'standard' text 188 * mode (80x25). 189 */ 190 check_for_vga(pba.pba_iot, pba.pba_memt); 191 return; 192 } 193 194 enable_pci_devices(); 195 196 #if defined(_ATARIHW_) 197 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 198 #endif 199 200 printf("\n"); 201 202 config_found_ia(self, "pcibus", &pba, ataripcibusprint); 203 } 204 205 int 206 ataripcibusprint(void *aux, const char *name) 207 { 208 209 if (name == NULL) 210 return UNCONF; 211 return QUIET; 212 } 213 214 void 215 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 216 { 217 } 218 219 /* 220 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 221 * We only disable all devices here. Memory and I/O enabling is done 222 * later at pcibusattach. 223 */ 224 void 225 init_pci_bus(void) 226 { 227 pci_chipset_tag_t pc = NULL; /* XXX */ 228 pcitag_t tag; 229 pcireg_t csr; 230 int device, maxndevs; 231 uint32_t id; 232 233 tag = 0; 234 id = 0; 235 236 maxndevs = pci_bus_maxdevs(pc, 0); 237 238 for (device = 0; device < maxndevs; device++) { 239 240 tag = pci_make_tag(pc, 0, device, 0); 241 id = pci_conf_read(pc, tag, PCI_ID_REG); 242 if (id == 0 || id == 0xffffffff) 243 continue; 244 245 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 246 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 247 csr &= ~PCI_COMMAND_MASTER_ENABLE; 248 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 249 } 250 } 251 252 /* 253 * insert a new element in an existing list that the ID's (size in struct 254 * pci_memreg) are sorted. 255 */ 256 static void 257 insert_into_list(PCI_MEMREG *head, struct pci_memreg *elem) 258 { 259 struct pci_memreg *p, *q; 260 261 p = LIST_FIRST(head); 262 q = NULL; 263 264 for (; p != NULL && p->size < elem->size; 265 q = p, p = LIST_NEXT(p, link)) 266 ; 267 268 if (q == NULL) { 269 LIST_INSERT_HEAD(head, elem, link); 270 } else { 271 LIST_INSERT_AFTER(q, elem, link); 272 } 273 } 274 275 /* 276 * Test if a new selected area overlaps with an already (probably preselected) 277 * pci area. 278 */ 279 static int 280 overlap_pci_areas(struct pci_memreg *p, struct pci_memreg *self, u_int addr, 281 u_int size, u_int what) 282 { 283 struct pci_memreg *q; 284 285 if (p == NULL) 286 return 0; 287 288 q = p; 289 while (q != NULL) { 290 if ((q != self) && (q->csr & what)) { 291 if ((addr >= q->address) && 292 (addr < (q->address + q->size))) { 293 #ifdef DEBUG_PCI_MACHDEP 294 printf("\noverlap area dev %d reg 0x%02x " 295 "with dev %d reg 0x%02x", 296 self->dev, self->reg, q->dev, q->reg); 297 #endif 298 return 1; 299 } 300 if ((q->address >= addr) && 301 (q->address < (addr + size))) { 302 #ifdef DEBUG_PCI_MACHDEP 303 printf("\noverlap area dev %d reg 0x%02x " 304 "with dev %d reg 0x%02x", 305 self->dev, self->reg, q->dev, q->reg); 306 #endif 307 return 1; 308 } 309 } 310 q = LIST_NEXT(q, link); 311 } 312 return 0; 313 } 314 315 /* 316 * Enable memory and I/O on pci devices. Care about already enabled devices 317 * (probabaly by the console driver). 318 * 319 * The idea behind the following code is: 320 * We build a by sizes sorted list of the requirements of the different 321 * pci devices. After that we choose the start addresses of that areas 322 * in such a way that they are placed as closed as possible together. 323 */ 324 static void 325 enable_pci_devices(void) 326 { 327 PCI_MEMREG memlist; 328 PCI_MEMREG iolist; 329 struct pci_memreg *p, *q; 330 int dev, reg; 331 uint32_t id, class; 332 pcitag_t tag; 333 pcireg_t csr, address, mask; 334 pci_chipset_tag_t pc; 335 int sizecnt, membase_1m; 336 337 pc = 0; 338 csr = 0; 339 tag = 0; 340 341 LIST_INIT(&memlist); 342 LIST_INIT(&iolist); 343 344 /* 345 * first step: go through all devices and gather memory and I/O 346 * sizes 347 */ 348 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 349 350 tag = pci_make_tag(pc, 0, dev, 0); 351 id = pci_conf_read(pc, tag, PCI_ID_REG); 352 if (id == 0 || id == 0xffffffff) 353 continue; 354 355 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 356 357 /* 358 * special case: if a display card is found and memory is 359 * enabled preserve 128k at 0xa0000 as vga memory. 360 * XXX: if a display card is found without being enabled, 361 * leave it alone! You will usually only create conflicts 362 * by enabeling it. 363 */ 364 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 365 switch (PCI_CLASS(class)) { 366 case PCI_CLASS_PREHISTORIC: 367 case PCI_CLASS_DISPLAY: 368 if (csr & (PCI_COMMAND_MEM_ENABLE | 369 PCI_COMMAND_MASTER_ENABLE)) { 370 p = malloc(sizeof(struct pci_memreg), 371 M_TEMP, M_WAITOK); 372 memset(p, 0, sizeof(struct pci_memreg)); 373 p->dev = dev; 374 p->csr = csr; 375 p->tag = tag; 376 p->reg = 0; /* there is no register 377 about this */ 378 p->size = 0x20000; /* 128kByte */ 379 p->mask = 0xfffe0000; 380 p->address = 0xa0000; 381 382 insert_into_list(&memlist, p); 383 } else 384 continue; 385 } 386 387 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 388 address = pci_conf_read(pc, tag, reg); 389 pci_conf_write(pc, tag, reg, 0xffffffff); 390 mask = pci_conf_read(pc, tag, reg); 391 pci_conf_write(pc, tag, reg, address); 392 if (mask == 0) 393 continue; /* Register unused */ 394 395 p = malloc(sizeof(struct pci_memreg), 396 M_TEMP, M_WAITOK); 397 memset(p, 0, sizeof(struct pci_memreg)); 398 p->dev = dev; 399 p->csr = csr; 400 p->tag = tag; 401 p->reg = reg; 402 p->mask = mask; 403 p->address = 0; 404 405 if ((mask & PCI_MAPREG_TYPE_IO) != 0) { 406 p->size = PCI_MAPREG_IO_SIZE(mask); 407 408 /* 409 * Align IO if necessary 410 */ 411 if (p->size < PCI_MAPREG_IO_SIZE( 412 PCI_MACHDEP_IO_ALIGN_MASK)) { 413 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 414 p->size = PCI_MAPREG_IO_SIZE(p->mask); 415 } 416 417 /* 418 * if I/O is already enabled 419 * (probably by the console driver) 420 * save the address in order to take care 421 * about it later. 422 */ 423 if ((csr & PCI_COMMAND_IO_ENABLE) != 0) 424 p->address = address; 425 426 insert_into_list(&iolist, p); 427 } else { 428 p->size = PCI_MAPREG_MEM_SIZE(mask); 429 430 /* 431 * Align memory if necessary 432 */ 433 if (p->size < PCI_MAPREG_IO_SIZE( 434 PCI_MACHDEP_MEM_ALIGN_MASK)) { 435 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 436 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 437 } 438 439 /* 440 * if memory is already enabled 441 * (probably by the console driver) 442 * save the address in order to take care 443 * about it later. 444 */ 445 if ((csr & PCI_COMMAND_MEM_ENABLE) != 0) 446 p->address = address; 447 448 insert_into_list(&memlist, p); 449 450 if (PCI_MAPREG_MEM_TYPE(mask) == 451 PCI_MAPREG_MEM_TYPE_64BIT) 452 reg++; 453 } 454 } 455 456 #if defined(_ATARIHW_) 457 /* 458 * Both interrupt pin & line are set to the device (== slot) 459 * number. This makes sense on the atari Hades because the 460 * individual slots are hard-wired to a specific MFP-pin. 461 */ 462 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 463 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 464 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 465 #else 466 /* 467 * On the Milan, we accept the BIOS's choice. 468 */ 469 /* 470 * ..except the secondary IDE interrupt that 471 * the BIOS doesn't setup. 472 */ 473 #define PIIX_PCIB_MBIRQ0 0x70 474 if ((PCI_VENDOR(id) == PCI_VENDOR_INTEL) && 475 (PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_82371FB_ISA)) { 476 /* 477 * Set Interrupt Routing for MBIRQ0 to IRQ15. 478 * Note Milan's ROM bootloader v1.2 and v1.4 479 * incorrectly set MBIRQ0 to IRQ14 (not 15) 480 * and unused MBIRQ1 to IRQ 15, 481 * so explicitly disable MBIRQ1. 482 */ 483 csr = pci_conf_read(pc, tag, PIIX_PCIB_MBIRQ0); 484 csr &= ~0x0000ffff; 485 /* MBIRQ1: disable, MBIRQ0: IRQ15 */ 486 csr |= 0x0000800f; 487 pci_conf_write(pc, tag, PIIX_PCIB_MBIRQ0, csr); 488 #ifdef DEBUG_PCI_MACHDEP 489 printf("\npcib0: enable and route MBIRQ0 to irq 15\n"); 490 #endif 491 } 492 #endif 493 } 494 495 /* 496 * second step: calculate the memory and I/O addresses beginning from 497 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 498 * 499 * begin with memory list 500 */ 501 502 address = PCI_MEM_START; 503 sizecnt = 0; 504 membase_1m = 0; 505 p = LIST_FIRST(&memlist); 506 while (p != NULL) { 507 if ((p->csr & PCI_COMMAND_MEM_ENABLE) == 0) { 508 if (PCI_MAPREG_MEM_TYPE(p->mask) == 509 PCI_MAPREG_MEM_TYPE_32BIT_1M) { 510 if (p->size > membase_1m) 511 membase_1m = p->size; 512 do { 513 p->address = membase_1m; 514 membase_1m += p->size; 515 } while (overlap_pci_areas(LIST_FIRST(&memlist), 516 p, p->address, p->size, 517 PCI_COMMAND_MEM_ENABLE)); 518 if (membase_1m > 0x00100000) { 519 /* 520 * Should we panic here? 521 */ 522 printf("\npcibus0: dev %d reg %d:" 523 " memory not configured", 524 p->dev, p->reg); 525 p->reg = 0; 526 } 527 } else { 528 if (sizecnt && (p->size > sizecnt)) 529 sizecnt = 530 ((p->size + sizecnt) & p->mask) & 531 PCI_MAPREG_MEM_ADDR_MASK; 532 if (sizecnt > address) { 533 address = sizecnt; 534 sizecnt = 0; 535 } 536 537 do { 538 p->address = address + sizecnt; 539 sizecnt += p->size; 540 } while (overlap_pci_areas(LIST_FIRST(&memlist), 541 p, p->address, p->size, 542 PCI_COMMAND_MEM_ENABLE)); 543 544 if ((address + sizecnt) > PCI_MEM_END) { 545 /* 546 * Should we panic here? 547 */ 548 printf("\npcibus0: dev %d reg %d:" 549 " memory not configured", 550 p->dev, p->reg); 551 p->reg = 0; 552 } 553 } 554 if (p->reg > 0) { 555 pci_conf_write(pc, p->tag, p->reg, p->address); 556 csr = pci_conf_read(pc, p->tag, 557 PCI_COMMAND_STATUS_REG); 558 csr |= PCI_COMMAND_MEM_ENABLE | 559 PCI_COMMAND_MASTER_ENABLE; 560 pci_conf_write(pc, p->tag, 561 PCI_COMMAND_STATUS_REG, csr); 562 p->csr = csr; 563 } 564 } 565 p = LIST_NEXT(p, link); 566 } 567 568 /* 569 * now the I/O list 570 */ 571 572 address = PCI_IO_START; 573 sizecnt = 0; 574 p = LIST_FIRST(&iolist); 575 while (p != NULL) { 576 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 577 578 if (sizecnt && (p->size > sizecnt)) 579 sizecnt = ((p->size + sizecnt) & p->mask) & 580 PCI_MAPREG_IO_ADDR_MASK; 581 if (sizecnt > address) { 582 address = sizecnt; 583 sizecnt = 0; 584 } 585 586 do { 587 p->address = address + sizecnt; 588 sizecnt += p->size; 589 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, 590 p->address, p->size, PCI_COMMAND_IO_ENABLE)); 591 592 if ((address + sizecnt) > PCI_IO_END) { 593 /* 594 * Should we panic here? 595 */ 596 printf("\npcibus0: dev %d reg %d:" 597 " io not configured", 598 p->dev, p->reg); 599 } else { 600 pci_conf_write(pc, p->tag, p->reg, p->address); 601 csr = pci_conf_read(pc, p->tag, 602 PCI_COMMAND_STATUS_REG); 603 csr |= PCI_COMMAND_IO_ENABLE | 604 PCI_COMMAND_MASTER_ENABLE; 605 pci_conf_write(pc, p->tag, 606 PCI_COMMAND_STATUS_REG, csr); 607 p->csr = csr; 608 } 609 } 610 p = LIST_NEXT(p, link); 611 } 612 613 #ifdef DEBUG_PCI_MACHDEP 614 printf("\nI/O List:\n"); 615 p = LIST_FIRST(&iolist); 616 617 while (p != NULL) { 618 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", 619 p->dev, p->reg, p->size, p->address); 620 p = LIST_NEXT(p, link); 621 } 622 printf("\nMemlist:"); 623 p = LIST_FIRST(&memlist); 624 625 while (p != NULL) { 626 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", 627 p->dev, p->reg, p->size, p->address); 628 p = LIST_NEXT(p, link); 629 } 630 #endif 631 632 /* 633 * Free the lists 634 */ 635 p = LIST_FIRST(&iolist); 636 while (p != NULL) { 637 q = p; 638 LIST_REMOVE(q, link); 639 free(p, M_WAITOK); 640 p = LIST_FIRST(&iolist); 641 } 642 p = LIST_FIRST(&memlist); 643 while (p != NULL) { 644 q = p; 645 LIST_REMOVE(q, link); 646 free(p, M_WAITOK); 647 p = LIST_FIRST(&memlist); 648 } 649 } 650 651 pcitag_t 652 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 653 { 654 655 return (bus << 16) | (device << 11) | (function << 8); 656 } 657 658 void 659 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 660 { 661 662 if (bp != NULL) 663 *bp = (tag >> 16) & 0xff; 664 if (dp != NULL) 665 *dp = (tag >> 11) & 0x1f; 666 if (fp != NULL) 667 *fp = (tag >> 8) & 0x7; 668 } 669 670 int 671 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 672 { 673 int line = pa->pa_intrline; 674 675 #if defined(_MILANHW_) 676 /* 677 * On the Hades, the 'pin' info is useless. 678 */ 679 { 680 int pin = pa->pa_intrpin; 681 682 if (pin == 0) { 683 /* No IRQ used. */ 684 goto bad; 685 } 686 if (pin > PCI_INTERRUPT_PIN_MAX) { 687 printf("pci_intr_map: bad interrupt pin %d\n", pin); 688 goto bad; 689 } 690 } 691 #endif /* _MILANHW_ */ 692 693 /* 694 * According to the PCI-spec, 255 means `unknown' or `no connection'. 695 * Interpret this as 'no interrupt assigned'. 696 */ 697 if (line == 255) 698 goto bad; 699 700 /* 701 * Values are pretty useless on the Hades since all interrupt 702 * lines for a card are tied together and hardwired to a 703 * specific TT-MFP I/O port. 704 * On the Milan, they are tied to the ICU. 705 */ 706 #if defined(_MILANHW_) 707 if (line >= 16) { 708 printf("pci_intr_map: bad interrupt line %d\n", line); 709 goto bad; 710 } 711 if (line == 2) { 712 printf("pci_intr_map: changed line 2 to line 9\n"); 713 line = 9; 714 } 715 /* Assume line == 0 means unassigned */ 716 if (line == 0) 717 goto bad; 718 #endif 719 *ihp = line; 720 return 0; 721 722 bad: 723 *ihp = -1; 724 return 1; 725 } 726 727 const char * 728 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 729 size_t len) 730 { 731 732 if (ih == -1) 733 panic("pci_intr_string: bogus handle 0x%x", ih); 734 735 snprintf(buf, len, "irq %d", ih); 736 return buf; 737 738 } 739 740 const struct evcnt * 741 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 742 { 743 744 /* XXX for now, no evcnt parent reported */ 745 return NULL; 746 } 747