1 /* $NetBSD: pci_machdep.c,v 1.41 2003/11/10 08:51:51 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.41 2003/11/10 08:51:51 wiz Exp $"); 36 37 #include "opt_mbtype.h" 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/time.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #define _ATARI_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <machine/cpu.h> 56 #include <machine/iomap.h> 57 #include <machine/mfp.h> 58 59 #include <atari/atari/device.h> 60 #include <atari/pci/pci_vga.h> 61 62 /* 63 * Sizes of pci memory and I/O area. 64 */ 65 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 66 #define PCI_IO_END 0x10000000 /* 256 MByte */ 67 68 /* 69 * We preserve some space at the begin of the pci area for 32BIT_1M 70 * devices and standard vga. 71 */ 72 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 73 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 74 I/O addresses up to 0xffff) */ 75 76 /* 77 * PCI memory and IO should be aligned acording to this masks 78 */ 79 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 80 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 81 82 /* 83 * Convert a PCI 'device' number to a slot number. 84 */ 85 #define DEV2SLOT(dev) (3 - dev) 86 87 /* 88 * Struct to hold the memory and I/O datas of the pci devices 89 */ 90 struct pci_memreg { 91 LIST_ENTRY(pci_memreg) link; 92 int dev; 93 pcitag_t tag; 94 pcireg_t reg, address, mask; 95 u_int32_t size; 96 u_int32_t csr; 97 }; 98 99 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 100 101 /* 102 * Entry points for PCI DMA. Use only the 'standard' functions. 103 */ 104 int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 105 bus_size_t, int, bus_dmamap_t *)); 106 struct atari_bus_dma_tag pci_bus_dma_tag = { 107 0, 108 #if defined(_ATARIHW_) 109 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 110 #else 111 0, 112 #endif 113 _bus_dmamap_create, 114 _bus_dmamap_destroy, 115 _bus_dmamap_load, 116 _bus_dmamap_load_mbuf, 117 _bus_dmamap_load_uio, 118 _bus_dmamap_load_raw, 119 _bus_dmamap_unload, 120 _bus_dmamap_sync, 121 }; 122 123 int pcibusprint __P((void *auxp, const char *)); 124 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 125 void pcibusattach __P((struct device *, struct device *, void *)); 126 127 static void enable_pci_devices __P((void)); 128 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 129 static int overlap_pci_areas __P((struct pci_memreg *p, 130 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 131 132 CFATTACH_DECL(pcib, sizeof(struct device), 133 pcibusmatch, pcibusattach, NULL, NULL); 134 135 /* 136 * We need some static storage to probe pci-busses for VGA cards during 137 * early console init. 138 */ 139 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 140 141 int 142 pcibusmatch(pdp, cfp, auxp) 143 struct device *pdp; 144 struct cfdata *cfp; 145 void *auxp; 146 { 147 static int nmatched = 0; 148 149 if (strcmp((char *)auxp, "pcib")) 150 return (0); /* Wrong number... */ 151 152 if(atari_realconfig == 0) 153 return (1); 154 155 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 156 /* 157 * Both Hades and Milan have only one pci bus 158 */ 159 if (nmatched) 160 return (0); 161 nmatched++; 162 return (1); 163 } 164 return (0); 165 } 166 167 void 168 pcibusattach(pdp, dp, auxp) 169 struct device *pdp, *dp; 170 void *auxp; 171 { 172 struct pcibus_attach_args pba; 173 174 pba.pba_busname = "pci"; 175 pba.pba_pc = NULL; 176 pba.pba_bus = 0; 177 pba.pba_bridgetag = NULL; 178 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 179 pba.pba_dmat = &pci_bus_dma_tag; 180 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 181 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 182 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 183 printf("leb_alloc_bus_space_tag failed!\n"); 184 return; 185 } 186 pba.pba_iot->base = PCI_IO_PHYS; 187 pba.pba_memt->base = PCI_MEM_PHYS; 188 189 if (dp == NULL) { 190 /* 191 * Scan the bus for a VGA-card that we support. If we 192 * find one, try to initialize it to a 'standard' text 193 * mode (80x25). 194 */ 195 check_for_vga(pba.pba_iot, pba.pba_memt); 196 return; 197 } 198 199 enable_pci_devices(); 200 201 #if defined(_ATARIHW_) 202 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 203 #endif 204 205 printf("\n"); 206 207 config_found(dp, &pba, pcibusprint); 208 } 209 210 int 211 pcibusprint(auxp, name) 212 void *auxp; 213 const char *name; 214 { 215 if(name == NULL) 216 return(UNCONF); 217 return(QUIET); 218 } 219 220 void 221 pci_attach_hook(parent, self, pba) 222 struct device *parent, *self; 223 struct pcibus_attach_args *pba; 224 { 225 } 226 227 /* 228 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 229 * We only disable all devices here. Memory and I/O enabling is done 230 * later at pcibusattach. 231 */ 232 void 233 init_pci_bus() 234 { 235 pci_chipset_tag_t pc = NULL; /* XXX */ 236 pcitag_t tag; 237 pcireg_t csr; 238 int device, id, maxndevs; 239 240 tag = 0; 241 id = 0; 242 243 maxndevs = pci_bus_maxdevs(pc, 0); 244 245 for (device = 0; device < maxndevs; device++) { 246 247 tag = pci_make_tag(pc, 0, device, 0); 248 id = pci_conf_read(pc, tag, PCI_ID_REG); 249 if (id == 0 || id == 0xffffffff) 250 continue; 251 252 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 253 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 254 csr &= ~PCI_COMMAND_MASTER_ENABLE; 255 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 256 } 257 } 258 259 /* 260 * insert a new element in an existing list that the ID's (size in struct 261 * pci_memreg) are sorted. 262 */ 263 static void 264 insert_into_list(head, elem) 265 PCI_MEMREG *head; 266 struct pci_memreg *elem; 267 { 268 struct pci_memreg *p, *q; 269 270 p = LIST_FIRST(head); 271 q = NULL; 272 273 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 274 275 if (q == NULL) { 276 LIST_INSERT_HEAD(head, elem, link); 277 } else { 278 LIST_INSERT_AFTER(q, elem, link); 279 } 280 } 281 282 /* 283 * Test if a new selected area overlaps with an already (probably preselected) 284 * pci area. 285 */ 286 static int 287 overlap_pci_areas(p, self, addr, size, what) 288 struct pci_memreg *p, *self; 289 u_int addr, size, what; 290 { 291 struct pci_memreg *q; 292 293 if (p == NULL) 294 return 0; 295 296 q = p; 297 while (q != NULL) { 298 if ((q != self) && (q->csr & what)) { 299 if ((addr >= q->address) && (addr < (q->address + q->size))) { 300 #ifdef DEBUG_PCI_MACHDEP 301 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 302 self->dev, self->reg, q->dev, q->reg); 303 #endif 304 return 1; 305 } 306 if ((q->address >= addr) && (q->address < (addr + size))) { 307 #ifdef DEBUG_PCI_MACHDEP 308 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 309 self->dev, self->reg, q->dev, q->reg); 310 #endif 311 return 1; 312 } 313 } 314 q = LIST_NEXT(q, link); 315 } 316 return 0; 317 } 318 319 /* 320 * Enable memory and I/O on pci devices. Care about already enabled devices 321 * (probabaly by the console driver). 322 * 323 * The idea behind the following code is: 324 * We build a by sizes sorted list of the requirements of the different 325 * pci devices. After that we choose the start addresses of that areas 326 * in such a way that they are placed as closed as possible together. 327 */ 328 static void 329 enable_pci_devices() 330 { 331 PCI_MEMREG memlist; 332 PCI_MEMREG iolist; 333 struct pci_memreg *p, *q; 334 int dev, reg, id, class; 335 pcitag_t tag; 336 pcireg_t csr, address, mask; 337 pci_chipset_tag_t pc; 338 int sizecnt, membase_1m; 339 340 pc = 0; 341 csr = 0; 342 tag = 0; 343 344 LIST_INIT(&memlist); 345 LIST_INIT(&iolist); 346 347 /* 348 * first step: go through all devices and gather memory and I/O 349 * sizes 350 */ 351 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 352 353 tag = pci_make_tag(pc, 0, dev, 0); 354 id = pci_conf_read(pc, tag, PCI_ID_REG); 355 if (id == 0 || id == 0xffffffff) 356 continue; 357 358 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 359 360 /* 361 * special case: if a display card is found and memory is enabled 362 * preserve 128k at 0xa0000 as vga memory. 363 * XXX: if a display card is found without being enabled, leave 364 * it alone! You will usually only create conflicts by enabeling 365 * it. 366 */ 367 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 368 switch (PCI_CLASS(class)) { 369 case PCI_CLASS_PREHISTORIC: 370 case PCI_CLASS_DISPLAY: 371 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 372 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 373 M_TEMP, M_WAITOK); 374 memset(p, '\0', sizeof(struct pci_memreg)); 375 p->dev = dev; 376 p->csr = csr; 377 p->tag = tag; 378 p->reg = 0; /* there is no register about this */ 379 p->size = 0x20000; /* 128kByte */ 380 p->mask = 0xfffe0000; 381 p->address = 0xa0000; 382 383 insert_into_list(&memlist, p); 384 } 385 else continue; 386 } 387 388 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 389 390 address = pci_conf_read(pc, tag, reg); 391 pci_conf_write(pc, tag, reg, 0xffffffff); 392 mask = pci_conf_read(pc, tag, reg); 393 pci_conf_write(pc, tag, reg, address); 394 if (mask == 0) 395 continue; /* Register unused */ 396 397 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 398 M_TEMP, M_WAITOK); 399 memset(p, '\0', sizeof(struct pci_memreg)); 400 p->dev = dev; 401 p->csr = csr; 402 p->tag = tag; 403 p->reg = reg; 404 p->mask = mask; 405 p->address = 0; 406 407 if (mask & PCI_MAPREG_TYPE_IO) { 408 p->size = PCI_MAPREG_IO_SIZE(mask); 409 410 /* 411 * Align IO if necessary 412 */ 413 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 414 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 415 p->size = PCI_MAPREG_IO_SIZE(p->mask); 416 } 417 418 /* 419 * if I/O is already enabled (probably by the console driver) 420 * save the address in order to take care about it later. 421 */ 422 if (csr & PCI_COMMAND_IO_ENABLE) 423 p->address = address; 424 425 insert_into_list(&iolist, p); 426 } else { 427 p->size = PCI_MAPREG_MEM_SIZE(mask); 428 429 /* 430 * Align memory if necessary 431 */ 432 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 433 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 434 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 435 } 436 437 /* 438 * if memory is already enabled (probably by the console driver) 439 * save the address in order to take care about it later. 440 */ 441 if (csr & PCI_COMMAND_MEM_ENABLE) 442 p->address = address; 443 444 insert_into_list(&memlist, p); 445 446 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 447 reg++; 448 } 449 } 450 451 452 #if defined(_ATARIHW_) 453 /* 454 * Both interrupt pin & line are set to the device (== slot) 455 * number. This makes sense on the atari Hades because the 456 * individual slots are hard-wired to a specific MFP-pin. 457 */ 458 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 459 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 460 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 461 #else 462 /* 463 * On the Milan, we accept the BIOS's choice. 464 */ 465 #endif 466 } 467 468 /* 469 * second step: calculate the memory and I/O addresses beginning from 470 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 471 * 472 * begin with memory list 473 */ 474 475 address = PCI_MEM_START; 476 sizecnt = 0; 477 membase_1m = 0; 478 p = LIST_FIRST(&memlist); 479 while (p != NULL) { 480 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 481 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 482 if (p->size > membase_1m) 483 membase_1m = p->size; 484 do { 485 p->address = membase_1m; 486 membase_1m += p->size; 487 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 488 p->size, PCI_COMMAND_MEM_ENABLE)); 489 if (membase_1m > 0x00100000) { 490 /* 491 * Should we panic here? 492 */ 493 printf("\npcibus0: dev %d reg %d: memory not configured", 494 p->dev, p->reg); 495 p->reg = 0; 496 } 497 } else { 498 499 if (sizecnt && (p->size > sizecnt)) 500 sizecnt = ((p->size + sizecnt) & p->mask) & 501 PCI_MAPREG_MEM_ADDR_MASK; 502 if (sizecnt > address) { 503 address = sizecnt; 504 sizecnt = 0; 505 } 506 507 do { 508 p->address = address + sizecnt; 509 sizecnt += p->size; 510 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 511 p->size, PCI_COMMAND_MEM_ENABLE)); 512 513 if ((address + sizecnt) > PCI_MEM_END) { 514 /* 515 * Should we panic here? 516 */ 517 printf("\npcibus0: dev %d reg %d: memory not configured", 518 p->dev, p->reg); 519 p->reg = 0; 520 } 521 } 522 if (p->reg > 0) { 523 pci_conf_write(pc, p->tag, p->reg, p->address); 524 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 525 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 526 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 527 p->csr = csr; 528 } 529 } 530 p = LIST_NEXT(p, link); 531 } 532 533 /* 534 * now the I/O list 535 */ 536 537 address = PCI_IO_START; 538 sizecnt = 0; 539 p = LIST_FIRST(&iolist); 540 while (p != NULL) { 541 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 542 543 if (sizecnt && (p->size > sizecnt)) 544 sizecnt = ((p->size + sizecnt) & p->mask) & 545 PCI_MAPREG_IO_ADDR_MASK; 546 if (sizecnt > address) { 547 address = sizecnt; 548 sizecnt = 0; 549 } 550 551 do { 552 p->address = address + sizecnt; 553 sizecnt += p->size; 554 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 555 p->size, PCI_COMMAND_IO_ENABLE)); 556 557 if ((address + sizecnt) > PCI_IO_END) { 558 /* 559 * Should we panic here? 560 */ 561 printf("\npcibus0: dev %d reg %d: io not configured", 562 p->dev, p->reg); 563 } else { 564 pci_conf_write(pc, p->tag, p->reg, p->address); 565 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 566 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 567 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 568 p->csr = csr; 569 } 570 } 571 p = LIST_NEXT(p, link); 572 } 573 574 #ifdef DEBUG_PCI_MACHDEP 575 printf("\nI/O List:\n"); 576 p = LIST_FIRST(&iolist); 577 578 while (p != NULL) { 579 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 580 p->reg, p->size, p->address); 581 p = LIST_NEXT(p, link); 582 } 583 printf("\nMemlist:"); 584 p = LIST_FIRST(&memlist); 585 586 while (p != NULL) { 587 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 588 p->reg, p->size, p->address); 589 p = LIST_NEXT(p, link); 590 } 591 #endif 592 593 /* 594 * Free the lists 595 */ 596 p = LIST_FIRST(&iolist); 597 while (p != NULL) { 598 q = p; 599 LIST_REMOVE(q, link); 600 free(p, M_WAITOK); 601 p = LIST_FIRST(&iolist); 602 } 603 p = LIST_FIRST(&memlist); 604 while (p != NULL) { 605 q = p; 606 LIST_REMOVE(q, link); 607 free(p, M_WAITOK); 608 p = LIST_FIRST(&memlist); 609 } 610 } 611 612 pcitag_t 613 pci_make_tag(pc, bus, device, function) 614 pci_chipset_tag_t pc; 615 int bus, device, function; 616 { 617 return ((bus << 16) | (device << 11) | (function << 8)); 618 } 619 620 void 621 pci_decompose_tag(pc, tag, bp, dp, fp) 622 pci_chipset_tag_t pc; 623 pcitag_t tag; 624 int *bp, *dp, *fp; 625 { 626 627 if (bp != NULL) 628 *bp = (tag >> 16) & 0xff; 629 if (dp != NULL) 630 *dp = (tag >> 11) & 0x1f; 631 if (fp != NULL) 632 *fp = (tag >> 8) & 0x7; 633 } 634 635 int 636 pci_intr_map(pa, ihp) 637 struct pci_attach_args *pa; 638 pci_intr_handle_t *ihp; 639 { 640 int line = pa->pa_intrline; 641 642 #if defined(_MILANHW_) 643 /* 644 * On the Hades, the 'pin' info is useless. 645 */ 646 { 647 int pin = pa->pa_intrpin; 648 649 if (pin == 0) { 650 /* No IRQ used. */ 651 goto bad; 652 } 653 if (pin > PCI_INTERRUPT_PIN_MAX) { 654 printf("pci_intr_map: bad interrupt pin %d\n", pin); 655 goto bad; 656 } 657 } 658 #endif /* _MILANHW_ */ 659 660 /* 661 * According to the PCI-spec, 255 means `unknown' or `no connection'. 662 * Interpret this as 'no interrupt assigned'. 663 */ 664 if (line == 255) 665 goto bad; 666 667 /* 668 * Values are pretty useless on the Hades since all interrupt 669 * lines for a card are tied together and hardwired to a 670 * specific TT-MFP I/O port. 671 * On the Milan, they are tied to the ICU. 672 */ 673 #if defined(_MILANHW_) 674 if (line >= 16) { 675 printf("pci_intr_map: bad interrupt line %d\n", line); 676 goto bad; 677 } 678 if (line == 2) { 679 printf("pci_intr_map: changed line 2 to line 9\n"); 680 line = 9; 681 } 682 /* Assume line == 0 means unassigned */ 683 if (line == 0) 684 goto bad; 685 #endif 686 *ihp = line; 687 return 0; 688 689 bad: 690 *ihp = -1; 691 return 1; 692 } 693 694 const char * 695 pci_intr_string(pc, ih) 696 pci_chipset_tag_t pc; 697 pci_intr_handle_t ih; 698 { 699 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 700 701 if (ih == -1) 702 panic("pci_intr_string: bogus handle 0x%x", ih); 703 704 sprintf(irqstr, "irq %d", ih); 705 return (irqstr); 706 707 } 708 709 const struct evcnt * 710 pci_intr_evcnt(pc, ih) 711 pci_chipset_tag_t pc; 712 pci_intr_handle_t ih; 713 { 714 715 /* XXX for now, no evcnt parent reported */ 716 return NULL; 717 } 718