1 /* $NetBSD: zs.c,v 1.56 2008/04/29 06:53:01 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)zs.c 8.1 (Berkeley) 7/19/93 42 */ 43 44 /*- 45 * Copyright (c) 1995 The NetBSD Foundation, Inc. (Atari modifications) 46 * All rights reserved. 47 * 48 * This code is derived from software contributed to The NetBSD Foundation 49 * by Leo Weppelman. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 61 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 62 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 63 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 64 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 65 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 66 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 67 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 68 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 69 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 70 * POSSIBILITY OF SUCH DAMAGE. 71 */ 72 73 /* 74 * Zilog Z8530 (ZSCC) driver. 75 * 76 * Runs two tty ports (modem2 and serial2) on zs0. 77 * 78 * This driver knows far too much about chip to usage mappings. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.56 2008/04/29 06:53:01 martin Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/proc.h> 87 #include <sys/device.h> 88 #include <sys/conf.h> 89 #include <sys/file.h> 90 #include <sys/ioctl.h> 91 #include <sys/malloc.h> 92 #include <sys/tty.h> 93 #include <sys/time.h> 94 #include <sys/kernel.h> 95 #include <sys/syslog.h> 96 #include <sys/kauth.h> 97 98 #include <machine/cpu.h> 99 #include <machine/iomap.h> 100 #include <machine/scu.h> 101 #include <machine/mfp.h> 102 #include <atari/dev/ym2149reg.h> 103 104 #include <dev/ic/z8530reg.h> 105 #include <atari/dev/zsvar.h> 106 #include "zs.h" 107 #if NZS > 1 108 #error "This driver supports only 1 85C30!" 109 #endif 110 111 #if NZS > 0 112 113 #define PCLK (8053976) /* PCLK pin input clock rate */ 114 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 115 116 #define splzs spl5 117 118 /* 119 * Software state per found chip. 120 */ 121 struct zs_softc { 122 struct device zi_dev; /* base device */ 123 volatile struct zsdevice *zi_zs; /* chip registers */ 124 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 125 }; 126 127 static u_char cb_scheduled = 0; /* Already asked for callback? */ 128 /* 129 * Define the registers for a closed port 130 */ 131 static u_char zs_init_regs[16] = { 132 /* 0 */ 0, 133 /* 1 */ 0, 134 /* 2 */ 0x60, 135 /* 3 */ 0, 136 /* 4 */ 0, 137 /* 5 */ 0, 138 /* 6 */ 0, 139 /* 7 */ 0, 140 /* 8 */ 0, 141 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 142 /* 10 */ ZSWR10_NRZ, 143 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 144 /* 12 */ 0, 145 /* 13 */ 0, 146 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 147 /* 15 */ 0 148 }; 149 150 /* 151 * Define the machine dependant clock frequencies 152 * If BRgen feeds sender/receiver we always use a 153 * divisor 16, therefor the division by 16 can as 154 * well be done here. 155 */ 156 static u_long zs_freqs_tt[] = { 157 /* 158 * Atari TT, RTxCB is generated by TT-MFP timer C, 159 * which is set to 307.2 kHz during initialisation 160 * and never changed afterwards. 161 */ 162 PCLK/16, /* BRgen, PCLK, divisor 16 */ 163 229500, /* BRgen, RTxCA, divisor 16 */ 164 3672000, /* RTxCA, from PCLK4 */ 165 0, /* TRxCA, external */ 166 167 PCLK/16, /* BRgen, PCLK, divisor 16 */ 168 19200, /* BRgen, RTxCB, divisor 16 */ 169 307200, /* RTxCB, from TT-MFP TCO */ 170 2457600 /* TRxCB, from BCLK */ 171 }; 172 173 static u_long zs_freqs_falcon[] = { 174 /* 175 * Atari Falcon, XXX no specs available, this might be wrong 176 */ 177 PCLK/16, /* BRgen, PCLK, divisor 16 */ 178 229500, /* BRgen, RTxCA, divisor 16 */ 179 3672000, /* RTxCA, ??? */ 180 0, /* TRxCA, external */ 181 182 PCLK/16, /* BRgen, PCLK, divisor 16 */ 183 229500, /* BRgen, RTxCB, divisor 16 */ 184 3672000, /* RTxCB, ??? */ 185 2457600 /* TRxCB, ??? */ 186 }; 187 188 static u_long zs_freqs_hades[] = { 189 /* 190 * XXX: Channel-A unchecked!!!!! 191 */ 192 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 193 229500, /* BRgen, RTxCA, divisor 16 */ 194 3672000, /* RTxCA, from PCLK4 */ 195 0, /* TRxCA, external */ 196 197 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 198 235550, /* BRgen, RTxCB, divisor 16 */ 199 3768800, /* RTxCB, 3.7688MHz */ 200 3768800 /* TRxCB, 3.7688MHz */ 201 }; 202 203 static u_long zs_freqs_generic[] = { 204 /* 205 * other machines, assume only PCLK is available 206 */ 207 PCLK/16, /* BRgen, PCLK, divisor 16 */ 208 0, /* BRgen, RTxCA, divisor 16 */ 209 0, /* RTxCA, unknown */ 210 0, /* TRxCA, unknown */ 211 212 PCLK/16, /* BRgen, PCLK, divisor 16 */ 213 0, /* BRgen, RTxCB, divisor 16 */ 214 0, /* RTxCB, unknown */ 215 0 /* TRxCB, unknown */ 216 }; 217 static u_long *zs_frequencies; 218 219 /* Definition of the driver for autoconfig. */ 220 static int zsmatch __P((struct device *, struct cfdata *, void *)); 221 static void zsattach __P((struct device *, struct device *, void *)); 222 223 CFATTACH_DECL(zs, sizeof(struct zs_softc), 224 zsmatch, zsattach, NULL, NULL); 225 226 extern struct cfdriver zs_cd; 227 228 /* {b,c}devsw[] function prototypes */ 229 dev_type_open(zsopen); 230 dev_type_close(zsclose); 231 dev_type_read(zsread); 232 dev_type_write(zswrite); 233 dev_type_ioctl(zsioctl); 234 dev_type_stop(zsstop); 235 dev_type_tty(zstty); 236 dev_type_poll(zspoll); 237 238 const struct cdevsw zs_cdevsw = { 239 zsopen, zsclose, zsread, zswrite, zsioctl, 240 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 241 }; 242 243 /* Interrupt handlers. */ 244 int zshard __P((long)); 245 static int zssoft __P((long)); 246 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 247 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 248 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 249 250 static struct zs_chanstate *zslist; 251 252 /* Routines called from other code. */ 253 static void zsstart __P((struct tty *)); 254 255 /* Routines purely local to this driver. */ 256 static void zsoverrun __P((int, long *, const char *)); 257 static int zsparam __P((struct tty *, struct termios *)); 258 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 259 static int zs_modem __P((struct zs_chanstate *, int, int)); 260 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 261 static void zs_shutdown __P((struct zs_chanstate *)); 262 263 static int zsshortcuts; /* number of "shortcut" software interrupts */ 264 265 static int 266 zsmatch(pdp, cfp, auxp) 267 struct device *pdp; 268 struct cfdata *cfp; 269 void *auxp; 270 { 271 static int zs_matched = 0; 272 273 if(strcmp("zs", auxp) || zs_matched) 274 return(0); 275 zs_matched = 1; 276 return(1); 277 } 278 279 /* 280 * Attach a found zs. 281 */ 282 static void 283 zsattach(parent, dev, aux) 284 struct device *parent; 285 struct device *dev; 286 void *aux; 287 { 288 register struct zs_softc *zi; 289 register struct zs_chanstate *cs; 290 register volatile struct zsdevice *addr; 291 char tmp; 292 293 addr = (struct zsdevice *)AD_SCC; 294 zi = (struct zs_softc *)dev; 295 zi->zi_zs = addr; 296 cs = zi->zi_cs; 297 298 /* 299 * Get the command register into a known state. 300 */ 301 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 302 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 303 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 304 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 305 306 /* 307 * Do a hardware reset. 308 */ 309 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 310 delay(50000); /*enough ? */ 311 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 312 313 /* 314 * Initialize both channels 315 */ 316 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 317 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 318 319 if(machineid & ATARI_TT) { 320 /* 321 * ininitialise TT-MFP timer C: 307200Hz 322 * timer C and D share one control register: 323 * bits 0-2 control timer D 324 * bits 4-6 control timer C 325 */ 326 int cr = MFP2->mf_tcdcr & 7; 327 MFP2->mf_tcdcr = cr; /* stop timer C */ 328 MFP2->mf_tcdr = 1; /* counter 1 */ 329 cr |= T_Q004 << 4; /* divisor 4 */ 330 MFP2->mf_tcdcr = cr; /* start timer C */ 331 /* 332 * enable scc related interrupts 333 */ 334 SCU->vme_mask |= SCU_SCC; 335 336 zs_frequencies = zs_freqs_tt; 337 } else if (machineid & ATARI_FALCON) { 338 zs_frequencies = zs_freqs_falcon; 339 } else if (machineid & ATARI_HADES) { 340 zs_frequencies = zs_freqs_hades; 341 } else { 342 zs_frequencies = zs_freqs_generic; 343 } 344 345 /* link into interrupt list with order (A,B) (B=A+1) */ 346 cs[0].cs_next = &cs[1]; 347 cs[1].cs_next = zslist; 348 zslist = cs; 349 350 cs->cs_unit = 0; 351 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 352 cs++; 353 cs->cs_unit = 1; 354 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 355 356 printf(": serial2 on channel a and modem2 on channel b\n"); 357 } 358 359 /* 360 * Open a zs serial port. 361 */ 362 int 363 zsopen(dev, flags, mode, l) 364 dev_t dev; 365 int flags; 366 int mode; 367 struct lwp *l; 368 { 369 register struct tty *tp; 370 register struct zs_chanstate *cs; 371 struct zs_softc *zi; 372 int unit = ZS_UNIT(dev); 373 int zs = unit >> 1; 374 int error, s; 375 376 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 377 return (ENXIO); 378 cs = &zi->zi_cs[unit & 1]; 379 380 /* 381 * When port A (ser02) is selected on the TT, make sure 382 * the port is enabled. 383 */ 384 if((machineid & ATARI_TT) && !(unit & 1)) 385 ym2149_ser2(1); 386 387 if (cs->cs_rbuf == NULL) { 388 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 389 M_WAITOK); 390 } 391 392 tp = cs->cs_ttyp; 393 if(tp == NULL) { 394 cs->cs_ttyp = tp = ttymalloc(); 395 tty_attach(tp); 396 tp->t_dev = dev; 397 tp->t_oproc = zsstart; 398 tp->t_param = zsparam; 399 } 400 401 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 402 return (EBUSY); 403 404 s = spltty(); 405 406 /* 407 * Do the following iff this is a first open. 408 */ 409 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 410 if(tp->t_ispeed == 0) { 411 tp->t_iflag = TTYDEF_IFLAG; 412 tp->t_oflag = TTYDEF_OFLAG; 413 tp->t_cflag = TTYDEF_CFLAG; 414 tp->t_lflag = TTYDEF_LFLAG; 415 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 416 } 417 ttychars(tp); 418 ttsetwater(tp); 419 420 (void)zsparam(tp, &tp->t_termios); 421 422 /* 423 * Turn on DTR. We must always do this, even if carrier is not 424 * present, because otherwise we'd have to use TIOCSDTR 425 * immediately after setting CLOCAL, which applications do not 426 * expect. We always assert DTR while the device is open 427 * unless explicitly requested to deassert it. 428 */ 429 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 430 /* May never get a status intr. if DCD already on. -gwr */ 431 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 432 tp->t_state |= TS_CARR_ON; 433 if(cs->cs_softcar) 434 tp->t_state |= TS_CARR_ON; 435 } 436 437 splx(s); 438 439 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 440 if (error) 441 goto bad; 442 443 error = tp->t_linesw->l_open(dev, tp); 444 if(error) 445 goto bad; 446 return (0); 447 448 bad: 449 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 450 /* 451 * We failed to open the device, and nobody else had it opened. 452 * Clean up the state as appropriate. 453 */ 454 zs_shutdown(cs); 455 } 456 return(error); 457 } 458 459 /* 460 * Close a zs serial port. 461 */ 462 int 463 zsclose(dev, flags, mode, l) 464 dev_t dev; 465 int flags; 466 int mode; 467 struct lwp *l; 468 { 469 register struct zs_chanstate *cs; 470 register struct tty *tp; 471 struct zs_softc *zi; 472 int unit = ZS_UNIT(dev); 473 474 zi = zs_cd.cd_devs[unit >> 1]; 475 cs = &zi->zi_cs[unit & 1]; 476 tp = cs->cs_ttyp; 477 478 tp->t_linesw->l_close(tp, flags); 479 ttyclose(tp); 480 481 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 482 /* 483 * Although we got a last close, the device may still be in 484 * use; e.g. if this was the dialout node, and there are still 485 * processes waiting for carrier on the non-dialout node. 486 */ 487 zs_shutdown(cs); 488 } 489 return (0); 490 } 491 492 /* 493 * Read/write zs serial port. 494 */ 495 int 496 zsread(dev, uio, flags) 497 dev_t dev; 498 struct uio *uio; 499 int flags; 500 { 501 register struct zs_chanstate *cs; 502 register struct zs_softc *zi; 503 register struct tty *tp; 504 int unit; 505 506 unit = ZS_UNIT(dev); 507 zi = zs_cd.cd_devs[unit >> 1]; 508 cs = &zi->zi_cs[unit & 1]; 509 tp = cs->cs_ttyp; 510 511 return(tp->t_linesw->l_read(tp, uio, flags)); 512 } 513 514 int 515 zswrite(dev, uio, flags) 516 dev_t dev; 517 struct uio *uio; 518 int flags; 519 { 520 register struct zs_chanstate *cs; 521 register struct zs_softc *zi; 522 register struct tty *tp; 523 int unit; 524 525 unit = ZS_UNIT(dev); 526 zi = zs_cd.cd_devs[unit >> 1]; 527 cs = &zi->zi_cs[unit & 1]; 528 tp = cs->cs_ttyp; 529 530 return(tp->t_linesw->l_write(tp, uio, flags)); 531 } 532 533 int 534 zspoll(dev, events, l) 535 dev_t dev; 536 int events; 537 struct lwp *l; 538 { 539 register struct zs_chanstate *cs; 540 register struct zs_softc *zi; 541 register struct tty *tp; 542 int unit; 543 544 unit = ZS_UNIT(dev); 545 zi = zs_cd.cd_devs[unit >> 1]; 546 cs = &zi->zi_cs[unit & 1]; 547 tp = cs->cs_ttyp; 548 549 return ((*tp->t_linesw->l_poll)(tp, events, l)); 550 } 551 552 struct tty * 553 zstty(dev) 554 dev_t dev; 555 { 556 register struct zs_chanstate *cs; 557 register struct zs_softc *zi; 558 int unit; 559 560 unit = ZS_UNIT(dev); 561 zi = zs_cd.cd_devs[unit >> 1]; 562 cs = &zi->zi_cs[unit & 1]; 563 return(cs->cs_ttyp); 564 } 565 566 /* 567 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 568 * channels are kept in (A,B) pairs. 569 * 570 * Do just a little, then get out; set a software interrupt if more 571 * work is needed. 572 * 573 * We deliberately ignore the vectoring Zilog gives us, and match up 574 * only the number of `reset interrupt under service' operations, not 575 * the order. 576 */ 577 578 int 579 zshard(sr) 580 long sr; 581 { 582 register struct zs_chanstate *a; 583 #define b (a + 1) 584 register volatile struct zschan *zc; 585 register int rr3, intflags = 0, v, i; 586 587 do { 588 intflags &= ~4; 589 for(a = zslist; a != NULL; a = b->cs_next) { 590 rr3 = ZS_READ(a->cs_zc, 3); 591 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 592 intflags |= 4|2; 593 zc = a->cs_zc; 594 i = a->cs_rbput; 595 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 596 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 597 intflags |= 1; 598 } 599 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 600 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 601 intflags |= 1; 602 } 603 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 604 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 605 intflags |= 1; 606 } 607 a->cs_rbput = i; 608 } 609 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 610 intflags |= 4|2; 611 zc = b->cs_zc; 612 i = b->cs_rbput; 613 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 614 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 615 intflags |= 1; 616 } 617 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 618 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 619 intflags |= 1; 620 } 621 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 622 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 623 intflags |= 1; 624 } 625 b->cs_rbput = i; 626 } 627 } 628 } while(intflags & 4); 629 #undef b 630 631 if(intflags & 1) { 632 if(BASEPRI(sr)) { 633 spl1(); 634 zsshortcuts++; 635 return(zssoft(sr)); 636 } 637 else if(!cb_scheduled) { 638 cb_scheduled++; 639 add_sicallback((si_farg)zssoft, 0, 0); 640 } 641 } 642 return(intflags & 2); 643 } 644 645 static int 646 zsrint(cs, zc) 647 register struct zs_chanstate *cs; 648 register volatile struct zschan *zc; 649 { 650 register int c; 651 652 /* 653 * First read the status, because read of the received char 654 * destroy the status of this char. 655 */ 656 c = ZS_READ(zc, 1); 657 c |= (zc->zc_data << 8); 658 659 /* clear receive error & interrupt condition */ 660 zc->zc_csr = ZSWR0_RESET_ERRORS; 661 zc->zc_csr = ZSWR0_CLR_INTR; 662 663 return(ZRING_MAKE(ZRING_RINT, c)); 664 } 665 666 static int 667 zsxint(cs, zc) 668 register struct zs_chanstate *cs; 669 register volatile struct zschan *zc; 670 { 671 register int i = cs->cs_tbc; 672 673 if(i == 0) { 674 zc->zc_csr = ZSWR0_RESET_TXINT; 675 zc->zc_csr = ZSWR0_CLR_INTR; 676 return(ZRING_MAKE(ZRING_XINT, 0)); 677 } 678 cs->cs_tbc = i - 1; 679 zc->zc_data = *cs->cs_tba++; 680 zc->zc_csr = ZSWR0_CLR_INTR; 681 return (0); 682 } 683 684 static int 685 zssint(cs, zc) 686 register struct zs_chanstate *cs; 687 register volatile struct zschan *zc; 688 { 689 register int rr0; 690 691 rr0 = zc->zc_csr; 692 zc->zc_csr = ZSWR0_RESET_STATUS; 693 zc->zc_csr = ZSWR0_CLR_INTR; 694 /* 695 * The chip's hardware flow control is, as noted in zsreg.h, 696 * busted---if the DCD line goes low the chip shuts off the 697 * receiver (!). If we want hardware CTS flow control but do 698 * not have it, and carrier is now on, turn HFC on; if we have 699 * HFC now but carrier has gone low, turn it off. 700 */ 701 if(rr0 & ZSRR0_DCD) { 702 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 703 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 704 cs->cs_creg[3] |= ZSWR3_HFC; 705 ZS_WRITE(zc, 3, cs->cs_creg[3]); 706 } 707 } 708 else { 709 if (cs->cs_creg[3] & ZSWR3_HFC) { 710 cs->cs_creg[3] &= ~ZSWR3_HFC; 711 ZS_WRITE(zc, 3, cs->cs_creg[3]); 712 } 713 } 714 return(ZRING_MAKE(ZRING_SINT, rr0)); 715 } 716 717 /* 718 * Print out a ring or fifo overrun error message. 719 */ 720 static void 721 zsoverrun(unit, ptime, what) 722 int unit; 723 long *ptime; 724 const char *what; 725 { 726 time_t cur_sec = time_second; 727 728 if(*ptime != cur_sec) { 729 *ptime = cur_sec; 730 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 731 (unit & 1) + 'a', what); 732 } 733 } 734 735 /* 736 * ZS software interrupt. Scan all channels for deferred interrupts. 737 */ 738 int 739 zssoft(sr) 740 long sr; 741 { 742 register struct zs_chanstate *cs; 743 register volatile struct zschan *zc; 744 register struct linesw *line; 745 register struct tty *tp; 746 register int get, n, c, cc, unit, s; 747 int retval = 0; 748 749 cb_scheduled = 0; 750 s = spltty(); 751 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 752 get = cs->cs_rbget; 753 again: 754 n = cs->cs_rbput; /* atomic */ 755 if(get == n) /* nothing more on this line */ 756 continue; 757 retval = 1; 758 unit = cs->cs_unit; /* set up to handle interrupts */ 759 zc = cs->cs_zc; 760 tp = cs->cs_ttyp; 761 line = tp->t_linesw; 762 /* 763 * Compute the number of interrupts in the receive ring. 764 * If the count is overlarge, we lost some events, and 765 * must advance to the first valid one. It may get 766 * overwritten if more data are arriving, but this is 767 * too expensive to check and gains nothing (we already 768 * lost out; all we can do at this point is trade one 769 * kind of loss for another). 770 */ 771 n -= get; 772 if(n > ZLRB_RING_SIZE) { 773 zsoverrun(unit, &cs->cs_rotime, "ring"); 774 get += n - ZLRB_RING_SIZE; 775 n = ZLRB_RING_SIZE; 776 } 777 while(--n >= 0) { 778 /* race to keep ahead of incoming interrupts */ 779 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 780 switch (ZRING_TYPE(c)) { 781 782 case ZRING_RINT: 783 c = ZRING_VALUE(c); 784 if(c & ZSRR1_DO) 785 zsoverrun(unit, &cs->cs_fotime, "fifo"); 786 cc = c >> 8; 787 if(c & ZSRR1_FE) 788 cc |= TTY_FE; 789 if(c & ZSRR1_PE) 790 cc |= TTY_PE; 791 line->l_rint(cc, tp); 792 break; 793 794 case ZRING_XINT: 795 /* 796 * Transmit done: change registers and resume, 797 * or clear BUSY. 798 */ 799 if(cs->cs_heldchange) { 800 int sps; 801 802 sps = splzs(); 803 c = zc->zc_csr; 804 if((c & ZSRR0_DCD) == 0) 805 cs->cs_preg[3] &= ~ZSWR3_HFC; 806 bcopy((void *)cs->cs_preg, 807 (void *)cs->cs_creg, 16); 808 zs_loadchannelregs(zc, cs->cs_creg); 809 splx(sps); 810 cs->cs_heldchange = 0; 811 if(cs->cs_heldtbc 812 && (tp->t_state & TS_TTSTOP) == 0) { 813 cs->cs_tbc = cs->cs_heldtbc - 1; 814 zc->zc_data = *cs->cs_tba++; 815 goto again; 816 } 817 } 818 tp->t_state &= ~TS_BUSY; 819 if(tp->t_state & TS_FLUSH) 820 tp->t_state &= ~TS_FLUSH; 821 else ndflush(&tp->t_outq,cs->cs_tba 822 - tp->t_outq.c_cf); 823 line->l_start(tp); 824 break; 825 826 case ZRING_SINT: 827 /* 828 * Status line change. HFC bit is run in 829 * hardware interrupt, to avoid locking 830 * at splzs here. 831 */ 832 c = ZRING_VALUE(c); 833 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 834 cc = (c & ZSRR0_DCD) != 0; 835 if(line->l_modem(tp, cc) == 0) 836 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 837 cc ? DMBIS : DMBIC); 838 } 839 cs->cs_rr0 = c; 840 break; 841 842 default: 843 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 844 unit >> 1, (unit & 1) + 'a', c); 845 break; 846 } 847 } 848 cs->cs_rbget = get; 849 goto again; 850 } 851 splx(s); 852 return (retval); 853 } 854 855 int 856 zsioctl(dev, cmd, data, flag, l) 857 dev_t dev; 858 u_long cmd; 859 void * data; 860 int flag; 861 struct lwp *l; 862 { 863 int unit = ZS_UNIT(dev); 864 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 865 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 866 register int error, s; 867 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 868 869 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 870 if(error != EPASSTHROUGH) 871 return(error); 872 873 error = ttioctl(tp, cmd, data, flag, l); 874 if(error !=EPASSTHROUGH) 875 return (error); 876 877 switch (cmd) { 878 case TIOCSBRK: 879 s = splzs(); 880 cs->cs_preg[5] |= ZSWR5_BREAK; 881 cs->cs_creg[5] |= ZSWR5_BREAK; 882 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 883 splx(s); 884 break; 885 case TIOCCBRK: 886 s = splzs(); 887 cs->cs_preg[5] &= ~ZSWR5_BREAK; 888 cs->cs_creg[5] &= ~ZSWR5_BREAK; 889 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 890 splx(s); 891 break; 892 case TIOCGFLAGS: { 893 int bits = 0; 894 895 if(cs->cs_softcar) 896 bits |= TIOCFLAG_SOFTCAR; 897 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 898 bits |= TIOCFLAG_CLOCAL; 899 if(cs->cs_creg[3] & ZSWR3_HFC) 900 bits |= TIOCFLAG_CRTSCTS; 901 *(int *)data = bits; 902 break; 903 } 904 case TIOCSFLAGS: { 905 int userbits = 0; 906 907 error = kauth_authorize_device_tty(l->l_cred, 908 KAUTH_DEVICE_TTY_PRIVSET, tp); 909 if(error != 0) 910 return (EPERM); 911 912 userbits = *(int *)data; 913 914 /* 915 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 916 # defaulting to software flow control. 917 */ 918 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 919 return(EINVAL); 920 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 921 return(ENODEV); 922 923 s = splzs(); 924 if((userbits & TIOCFLAG_SOFTCAR)) { 925 cs->cs_softcar = 1; /* turn on softcar */ 926 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 927 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 928 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 929 } 930 else if(userbits & TIOCFLAG_CLOCAL) { 931 cs->cs_softcar = 0; /* turn off softcar */ 932 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 933 cs->cs_creg[15] |= ZSWR15_DCD_IE; 934 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 935 tp->t_termios.c_cflag |= CLOCAL; 936 } 937 if(userbits & TIOCFLAG_CRTSCTS) { 938 cs->cs_preg[15] |= ZSWR15_CTS_IE; 939 cs->cs_creg[15] |= ZSWR15_CTS_IE; 940 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 941 cs->cs_preg[3] |= ZSWR3_HFC; 942 cs->cs_creg[3] |= ZSWR3_HFC; 943 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 944 tp->t_termios.c_cflag |= CRTSCTS; 945 } 946 else { 947 /* no mdmbuf, so we must want software flow control */ 948 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 949 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 950 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 951 cs->cs_preg[3] &= ~ZSWR3_HFC; 952 cs->cs_creg[3] &= ~ZSWR3_HFC; 953 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 954 tp->t_termios.c_cflag &= ~CRTSCTS; 955 } 956 splx(s); 957 break; 958 } 959 case TIOCSDTR: 960 zs_modem(cs, ZSWR5_DTR, DMBIS); 961 break; 962 case TIOCCDTR: 963 zs_modem(cs, ZSWR5_DTR, DMBIC); 964 break; 965 case TIOCMGET: 966 zs_modem(cs, 0, DMGET); 967 break; 968 case TIOCMSET: 969 case TIOCMBIS: 970 case TIOCMBIC: 971 default: 972 return (EPASSTHROUGH); 973 } 974 return (0); 975 } 976 977 /* 978 * Start or restart transmission. 979 */ 980 static void 981 zsstart(tp) 982 register struct tty *tp; 983 { 984 register struct zs_chanstate *cs; 985 register int s, nch; 986 int unit = ZS_UNIT(tp->t_dev); 987 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 988 989 cs = &zi->zi_cs[unit & 1]; 990 s = spltty(); 991 992 /* 993 * If currently active or delaying, no need to do anything. 994 */ 995 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 996 goto out; 997 998 /* 999 * If there are sleepers, and output has drained below low 1000 * water mark, awaken. 1001 */ 1002 ttypull(tp); 1003 1004 nch = ndqb(&tp->t_outq, 0); /* XXX */ 1005 if(nch) { 1006 register char *p = tp->t_outq.c_cf; 1007 1008 /* mark busy, enable tx done interrupts, & send first byte */ 1009 tp->t_state |= TS_BUSY; 1010 (void) splzs(); 1011 cs->cs_preg[1] |= ZSWR1_TIE; 1012 cs->cs_creg[1] |= ZSWR1_TIE; 1013 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1014 cs->cs_zc->zc_data = *p; 1015 cs->cs_tba = p + 1; 1016 cs->cs_tbc = nch - 1; 1017 } else { 1018 /* 1019 * Nothing to send, turn off transmit done interrupts. 1020 * This is useful if something is doing polled output. 1021 */ 1022 (void) splzs(); 1023 cs->cs_preg[1] &= ~ZSWR1_TIE; 1024 cs->cs_creg[1] &= ~ZSWR1_TIE; 1025 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1026 } 1027 out: 1028 splx(s); 1029 } 1030 1031 /* 1032 * Stop output, e.g., for ^S or output flush. 1033 */ 1034 void 1035 zsstop(tp, flag) 1036 register struct tty *tp; 1037 int flag; 1038 { 1039 register struct zs_chanstate *cs; 1040 register int s, unit = ZS_UNIT(tp->t_dev); 1041 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1042 1043 cs = &zi->zi_cs[unit & 1]; 1044 s = splzs(); 1045 if(tp->t_state & TS_BUSY) { 1046 /* 1047 * Device is transmitting; must stop it. 1048 */ 1049 cs->cs_tbc = 0; 1050 if ((tp->t_state & TS_TTSTOP) == 0) 1051 tp->t_state |= TS_FLUSH; 1052 } 1053 splx(s); 1054 } 1055 1056 static void 1057 zs_shutdown(cs) 1058 struct zs_chanstate *cs; 1059 { 1060 struct tty *tp = cs->cs_ttyp; 1061 int s; 1062 1063 s = splzs(); 1064 1065 /* 1066 * Hang up if necessary. Wait a bit, so the other side has time to 1067 * notice even if we immediately open the port again. 1068 */ 1069 if(tp->t_cflag & HUPCL) { 1070 zs_modem(cs, 0, DMSET); 1071 (void)tsleep((void *)cs, TTIPRI, ttclos, hz); 1072 } 1073 1074 /* Clear any break condition set with TIOCSBRK. */ 1075 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1076 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1077 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1078 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1079 } 1080 1081 /* 1082 * Drop all lines and cancel interrupts 1083 */ 1084 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1085 splx(s); 1086 } 1087 1088 /* 1089 * Set ZS tty parameters from termios. 1090 * 1091 * This routine makes use of the fact that only registers 1092 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1093 */ 1094 static int 1095 zsparam(tp, t) 1096 register struct tty *tp; 1097 register struct termios *t; 1098 { 1099 int unit = ZS_UNIT(tp->t_dev); 1100 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1101 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1102 int cdiv = 0, /* XXX gcc4 -Wuninitialized */ 1103 clkm = 0, /* XXX gcc4 -Wuninitialized */ 1104 brgm = 0, /* XXX gcc4 -Wuninitialized */ 1105 tcon = 0; /* XXX gcc4 -Wuninitialized */ 1106 register int tmp, tmp5, cflag, s; 1107 1108 tmp = t->c_ospeed; 1109 tmp5 = t->c_ispeed; 1110 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1111 return(EINVAL); 1112 if(tmp == 0) { 1113 /* stty 0 => drop DTR and RTS */ 1114 zs_modem(cs, 0, DMSET); 1115 return(0); 1116 } 1117 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1118 if (tmp < 0) 1119 return(EINVAL); 1120 tp->t_ispeed = tp->t_ospeed = tmp; 1121 1122 cflag = tp->t_cflag = t->c_cflag; 1123 if (cflag & CSTOPB) 1124 cdiv |= ZSWR4_TWOSB; 1125 else 1126 cdiv |= ZSWR4_ONESB; 1127 if (!(cflag & PARODD)) 1128 cdiv |= ZSWR4_EVENP; 1129 if (cflag & PARENB) 1130 cdiv |= ZSWR4_PARENB; 1131 1132 switch(cflag & CSIZE) { 1133 case CS5: 1134 tmp = ZSWR3_RX_5; 1135 tmp5 = ZSWR5_TX_5; 1136 break; 1137 case CS6: 1138 tmp = ZSWR3_RX_6; 1139 tmp5 = ZSWR5_TX_6; 1140 break; 1141 case CS7: 1142 tmp = ZSWR3_RX_7; 1143 tmp5 = ZSWR5_TX_7; 1144 break; 1145 case CS8: 1146 default: 1147 tmp = ZSWR3_RX_8; 1148 tmp5 = ZSWR5_TX_8; 1149 break; 1150 } 1151 tmp |= ZSWR3_RX_ENABLE; 1152 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1153 1154 /* 1155 * Block interrupts so that state will not 1156 * be altered until we are done setting it up. 1157 */ 1158 s = splzs(); 1159 cs->cs_preg[4] = cdiv; 1160 cs->cs_preg[11] = clkm; 1161 cs->cs_preg[12] = tcon; 1162 cs->cs_preg[13] = tcon >> 8; 1163 cs->cs_preg[14] = brgm; 1164 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1165 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1166 cs->cs_preg[10] = ZSWR10_NRZ; 1167 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1168 1169 /* 1170 * Output hardware flow control on the chip is horrendous: if 1171 * carrier detect drops, the receiver is disabled. Hence we 1172 * can only do this when the carrier is on. 1173 */ 1174 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1175 tmp |= ZSWR3_HFC; 1176 cs->cs_preg[3] = tmp; 1177 cs->cs_preg[5] = tmp5; 1178 1179 /* 1180 * If nothing is being transmitted, set up new current values, 1181 * else mark them as pending. 1182 */ 1183 if(cs->cs_heldchange == 0) { 1184 if (cs->cs_ttyp->t_state & TS_BUSY) { 1185 cs->cs_heldtbc = cs->cs_tbc; 1186 cs->cs_tbc = 0; 1187 cs->cs_heldchange = 1; 1188 } else { 1189 bcopy((void *)cs->cs_preg, (void *)cs->cs_creg, 16); 1190 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1191 } 1192 } 1193 splx(s); 1194 return (0); 1195 } 1196 1197 /* 1198 * search for the best matching baudrate 1199 */ 1200 static int 1201 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1202 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1203 { 1204 int bestdiff, bestbps, source; 1205 1206 bestdiff = bestbps = 0; 1207 unit = (unit & 1) << 2; 1208 for (source = 0; source < 4; ++source) { 1209 long freq = zs_frequencies[unit + source]; 1210 int diff, bps, div, clkm, brgm, tcon; 1211 1212 bps = div = clkm = brgm = tcon = 0; 1213 switch (source) { 1214 case 0: /* BRgen, PCLK */ 1215 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1216 break; 1217 case 1: /* BRgen, RTxC */ 1218 brgm = ZSWR14_BAUD_ENA; 1219 break; 1220 case 2: /* RTxC */ 1221 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1222 break; 1223 case 3: /* TRxC */ 1224 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1225 break; 1226 } 1227 switch (source) { 1228 case 0: 1229 case 1: 1230 div = ZSWR4_CLK_X16; 1231 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1232 tcon = BPS_TO_TCONST(freq, wanted); 1233 if (tcon < 0) 1234 tcon = 0; 1235 bps = TCONST_TO_BPS(freq, tcon); 1236 break; 1237 case 2: 1238 case 3: 1239 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1240 int b2 = freq / 32, d2 = abs(b2 - wanted); 1241 int b3 = freq / 64, d3 = abs(b3 - wanted); 1242 1243 if (d1 < d2 && d1 < d3) { 1244 div = ZSWR4_CLK_X16; 1245 bps = b1; 1246 } else if (d2 < d3 && d2 < d1) { 1247 div = ZSWR4_CLK_X32; 1248 bps = b2; 1249 } else { 1250 div = ZSWR4_CLK_X64; 1251 bps = b3; 1252 } 1253 brgm = tcon = 0; 1254 break; 1255 } 1256 } 1257 diff = abs(bps - wanted); 1258 if (!source || diff < bestdiff) { 1259 *divisor = div; 1260 *clockmode = clkm; 1261 *brgenmode = brgm; 1262 *timeconst = tcon; 1263 bestbps = bps; 1264 bestdiff = diff; 1265 if (diff == 0) 1266 break; 1267 } 1268 } 1269 /* Allow deviations upto 5% */ 1270 if (20 * bestdiff > wanted) 1271 return -1; 1272 return bestbps; 1273 } 1274 1275 /* 1276 * Raise or lower modem control (DTR/RTS) signals. If a character is 1277 * in transmission, the change is deferred. 1278 */ 1279 static int 1280 zs_modem(cs, bits, how) 1281 struct zs_chanstate *cs; 1282 int bits, how; 1283 { 1284 int s, mbits; 1285 1286 bits &= ZSWR5_DTR | ZSWR5_RTS; 1287 1288 s = splzs(); 1289 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1290 1291 switch(how) { 1292 case DMSET: 1293 mbits = bits; 1294 break; 1295 case DMBIS: 1296 mbits |= bits; 1297 break; 1298 case DMBIC: 1299 mbits &= ~bits; 1300 break; 1301 case DMGET: 1302 splx(s); 1303 return(mbits); 1304 } 1305 1306 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1307 if(cs->cs_heldchange == 0) { 1308 if(cs->cs_ttyp->t_state & TS_BUSY) { 1309 cs->cs_heldtbc = cs->cs_tbc; 1310 cs->cs_tbc = 0; 1311 cs->cs_heldchange = 1; 1312 } 1313 else { 1314 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1315 } 1316 } 1317 splx(s); 1318 return(0); 1319 } 1320 1321 /* 1322 * Write the given register set to the given zs channel in the proper order. 1323 * The channel must not be transmitting at the time. The receiver will 1324 * be disabled for the time it takes to write all the registers. 1325 */ 1326 static void 1327 zs_loadchannelregs(zc, reg) 1328 volatile struct zschan *zc; 1329 u_char *reg; 1330 { 1331 int i; 1332 1333 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1334 i = zc->zc_data; /* drain fifo */ 1335 i = zc->zc_data; 1336 i = zc->zc_data; 1337 ZS_WRITE(zc, 4, reg[4]); 1338 ZS_WRITE(zc, 10, reg[10]); 1339 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1340 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1341 ZS_WRITE(zc, 1, reg[1]); 1342 ZS_WRITE(zc, 9, reg[9]); 1343 ZS_WRITE(zc, 11, reg[11]); 1344 ZS_WRITE(zc, 12, reg[12]); 1345 ZS_WRITE(zc, 13, reg[13]); 1346 ZS_WRITE(zc, 14, reg[14]); 1347 ZS_WRITE(zc, 15, reg[15]); 1348 ZS_WRITE(zc, 3, reg[3]); 1349 ZS_WRITE(zc, 5, reg[5]); 1350 } 1351 #endif /* NZS > 1 */ 1352