1 /* $NetBSD: zs.c,v 1.21 1996/06/18 05:55:02 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49 /* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/proc.h> 59 #include <sys/device.h> 60 #include <sys/conf.h> 61 #include <sys/file.h> 62 #include <sys/ioctl.h> 63 #include <sys/malloc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/kernel.h> 67 #include <sys/syslog.h> 68 69 #include <machine/cpu.h> 70 #include <machine/iomap.h> 71 #include <machine/scu.h> 72 #include <machine/mfp.h> 73 #include <atari/dev/ym2149reg.h> 74 75 #include <dev/ic/z8530reg.h> 76 #include <atari/dev/zsvar.h> 77 #include "zs.h" 78 #if NZS > 1 79 #error "This driver supports only 1 85C30!" 80 #endif 81 82 #if NZS > 0 83 84 #define PCLK (8053976) /* PCLK pin input clock rate */ 85 86 #define splzs spl5 87 88 /* 89 * Software state per found chip. 90 */ 91 struct zs_softc { 92 struct device zi_dev; /* base device */ 93 volatile struct zsdevice *zi_zs; /* chip registers */ 94 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 95 }; 96 97 static u_char cb_scheduled = 0; /* Already asked for callback? */ 98 /* 99 * Define the registers for a closed port 100 */ 101 static u_char zs_init_regs[16] = { 102 /* 0 */ 0, 103 /* 1 */ 0, 104 /* 2 */ 0x60, 105 /* 3 */ 0, 106 /* 4 */ 0, 107 /* 5 */ 0, 108 /* 6 */ 0, 109 /* 7 */ 0, 110 /* 8 */ 0, 111 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 112 /* 10 */ ZSWR10_NRZ, 113 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 114 /* 12 */ 0, 115 /* 13 */ 0, 116 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 117 /* 15 */ 0 118 }; 119 120 /* 121 * Define the machine dependant clock frequencies 122 * If BRgen feeds sender/receiver we always use a 123 * divisor 16, therefor the division by 16 can as 124 * well be done here. 125 */ 126 static u_long zs_freqs_tt[] = { 127 /* 128 * Atari TT, RTxCB is generated by TT-MFP timer C, 129 * which is set to 307.2KHz during initialisation 130 * and never changed afterwards. 131 */ 132 PCLK/16, /* BRgen, PCLK, divisor 16 */ 133 229500, /* BRgen, RTxCA, divisor 16 */ 134 3672000, /* RTxCA, from PCLK4 */ 135 0, /* TRxCA, external */ 136 137 PCLK/16, /* BRgen, PCLK, divisor 16 */ 138 19200, /* BRgen, RTxCB, divisor 16 */ 139 307200, /* RTxCB, from TT-MFP TCO */ 140 2457600 /* TRxCB, from BCLK */ 141 }; 142 static u_long zs_freqs_falcon[] = { 143 /* 144 * Atari Falcon, XXX no specs available, this might be wrong 145 */ 146 PCLK/16, /* BRgen, PCLK, divisor 16 */ 147 229500, /* BRgen, RTxCA, divisor 16 */ 148 3672000, /* RTxCA, ??? */ 149 0, /* TRxCA, external */ 150 151 PCLK/16, /* BRgen, PCLK, divisor 16 */ 152 229500, /* BRgen, RTxCB, divisor 16 */ 153 3672000, /* RTxCB, ??? */ 154 2457600 /* TRxCB, ??? */ 155 }; 156 static u_long zs_freqs_generic[] = { 157 /* 158 * other machines, assume only PCLK is available 159 */ 160 PCLK/16, /* BRgen, PCLK, divisor 16 */ 161 0, /* BRgen, RTxCA, divisor 16 */ 162 0, /* RTxCA, unknown */ 163 0, /* TRxCA, unknown */ 164 165 PCLK/16, /* BRgen, PCLK, divisor 16 */ 166 0, /* BRgen, RTxCB, divisor 16 */ 167 0, /* RTxCB, unknown */ 168 0 /* TRxCB, unknown */ 169 }; 170 static u_long *zs_frequencies; 171 172 /* Definition of the driver for autoconfig. */ 173 static int zsmatch __P((struct device *, void *, void *)); 174 static void zsattach __P((struct device *, struct device *, void *)); 175 176 struct cfattach zs_ca = { 177 sizeof(struct zs_softc), zsmatch, zsattach 178 }; 179 180 struct cfdriver zs_cd = { 181 NULL, "zs", DV_TTY, NULL, 0 182 }; 183 184 /* {b,c}devsw[] function prototypes */ 185 dev_type_open(zsopen); 186 dev_type_close(zsclose); 187 dev_type_read(zsread); 188 dev_type_write(zswrite); 189 dev_type_ioctl(zsioctl); 190 dev_type_tty(zstty); 191 192 /* Interrupt handlers. */ 193 int zshard __P((long)); 194 static int zssoft __P((long)); 195 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 196 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 197 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 198 199 static struct zs_chanstate *zslist; 200 201 /* Routines called from other code. */ 202 static void zsstart __P((struct tty *)); 203 void zsstop __P((struct tty *, int)); 204 205 /* Routines purely local to this driver. */ 206 static void zsoverrun __P((int, long *, char *)); 207 static int zsparam __P((struct tty *, struct termios *)); 208 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 209 static int zs_modem __P((struct zs_chanstate *, int, int)); 210 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 211 212 static int zsshortcuts; /* number of "shortcut" software interrupts */ 213 214 static int 215 zsmatch(pdp, match, auxp) 216 struct device *pdp; 217 void *match, *auxp; 218 { 219 struct cfdata *cfp = match; 220 221 if(strcmp("zs", auxp) || cfp->cf_unit != 0) 222 return(0); 223 return(1); 224 } 225 226 /* 227 * Attach a found zs. 228 */ 229 static void 230 zsattach(parent, dev, aux) 231 struct device *parent; 232 struct device *dev; 233 void *aux; 234 { 235 register struct zs_softc *zi; 236 register struct zs_chanstate *cs; 237 register volatile struct zsdevice *addr; 238 char tmp; 239 240 addr = (struct zsdevice *)AD_SCC; 241 zi = (struct zs_softc *)dev; 242 zi->zi_zs = addr; 243 cs = zi->zi_cs; 244 245 /* 246 * Get the command register into a known state. 247 */ 248 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 249 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 250 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 251 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 252 253 /* 254 * Do a hardware reset. 255 */ 256 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 257 delay(50000); /*enough ? */ 258 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 259 260 /* 261 * Initialize both channels 262 */ 263 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 264 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 265 266 if(machineid & ATARI_TT) { 267 /* 268 * ininitialise TT-MFP timer C: 307200Hz 269 * timer C and D share one control register: 270 * bits 0-2 control timer D 271 * bits 4-6 control timer C 272 */ 273 int cr = MFP2->mf_tcdcr & 7; 274 MFP2->mf_tcdcr = cr; /* stop timer C */ 275 MFP2->mf_tcdr = 1; /* counter 1 */ 276 cr |= T_Q004 << 4; /* divisor 4 */ 277 MFP2->mf_tcdcr = cr; /* start timer C */ 278 /* 279 * enable scc related interrupts 280 */ 281 SCU->sys_mask |= SCU_SCC; 282 283 zs_frequencies = zs_freqs_tt; 284 } else if (machineid & ATARI_FALCON) { 285 zs_frequencies = zs_freqs_falcon; 286 } else { 287 zs_frequencies = zs_freqs_generic; 288 } 289 290 /* link into interrupt list with order (A,B) (B=A+1) */ 291 cs[0].cs_next = &cs[1]; 292 cs[1].cs_next = zslist; 293 zslist = cs; 294 295 cs->cs_unit = 0; 296 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 297 cs++; 298 cs->cs_unit = 1; 299 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 300 301 printf(": serial2 on channel a and modem2 on channel b\n"); 302 } 303 304 /* 305 * Open a zs serial port. 306 */ 307 int 308 zsopen(dev, flags, mode, p) 309 dev_t dev; 310 int flags; 311 int mode; 312 struct proc *p; 313 { 314 register struct tty *tp; 315 register struct zs_chanstate *cs; 316 struct zs_softc *zi; 317 int unit = ZS_UNIT(dev); 318 int zs = unit >> 1; 319 int error, s; 320 321 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 322 return (ENXIO); 323 cs = &zi->zi_cs[unit & 1]; 324 325 /* 326 * When port A (ser02) is selected on the TT, make sure 327 * the port is enabled. 328 */ 329 if((machineid & ATARI_TT) && !(unit & 1)) 330 ym2149_ser2_select(); 331 332 if (cs->cs_rbuf == NULL) { 333 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 334 M_WAITOK); 335 } 336 337 tp = cs->cs_ttyp; 338 if(tp == NULL) { 339 cs->cs_ttyp = tp = ttymalloc(); 340 tty_attach(tp); 341 tp->t_dev = dev; 342 tp->t_oproc = zsstart; 343 tp->t_param = zsparam; 344 } 345 346 s = spltty(); 347 if((tp->t_state & TS_ISOPEN) == 0) { 348 ttychars(tp); 349 if(tp->t_ispeed == 0) { 350 tp->t_iflag = TTYDEF_IFLAG; 351 tp->t_oflag = TTYDEF_OFLAG; 352 tp->t_cflag = TTYDEF_CFLAG; 353 tp->t_lflag = TTYDEF_LFLAG; 354 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 355 } 356 (void)zsparam(tp, &tp->t_termios); 357 ttsetwater(tp); 358 } 359 else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 360 splx(s); 361 return (EBUSY); 362 } 363 error = 0; 364 for(;;) { 365 /* loop, turning on the device, until carrier present */ 366 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 367 368 /* May never get a status intr. if DCD already on. -gwr */ 369 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 370 tp->t_state |= TS_CARR_ON; 371 if(cs->cs_softcar) 372 tp->t_state |= TS_CARR_ON; 373 if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL || 374 tp->t_state & TS_CARR_ON) 375 break; 376 tp->t_state |= TS_WOPEN; 377 if((error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH, 378 ttopen, 0)) != 0) { 379 if(!(tp->t_state & TS_ISOPEN)) { 380 zs_modem(cs, 0, DMSET); 381 tp->t_state &= ~TS_WOPEN; 382 ttwakeup(tp); 383 } 384 splx(s); 385 return error; 386 } 387 } 388 splx(s); 389 if(error == 0) 390 error = linesw[tp->t_line].l_open(dev, tp); 391 if(error) 392 zs_modem(cs, 0, DMSET); 393 return(error); 394 } 395 396 /* 397 * Close a zs serial port. 398 */ 399 int 400 zsclose(dev, flags, mode, p) 401 dev_t dev; 402 int flags; 403 int mode; 404 struct proc *p; 405 { 406 register struct zs_chanstate *cs; 407 register struct tty *tp; 408 struct zs_softc *zi; 409 int unit = ZS_UNIT(dev); 410 int s; 411 412 zi = zs_cd.cd_devs[unit >> 1]; 413 cs = &zi->zi_cs[unit & 1]; 414 tp = cs->cs_ttyp; 415 linesw[tp->t_line].l_close(tp, flags); 416 if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN || 417 (tp->t_state & TS_ISOPEN) == 0) { 418 zs_modem(cs, 0, DMSET); 419 /* hold low for 1 second */ 420 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 421 } 422 if(cs->cs_creg[5] & ZSWR5_BREAK) { 423 s = splzs(); 424 cs->cs_preg[5] &= ~ZSWR5_BREAK; 425 cs->cs_creg[5] &= ~ZSWR5_BREAK; 426 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 427 splx(s); 428 } 429 ttyclose(tp); 430 431 /* 432 * Drop all lines and cancel interrupts 433 */ 434 s = splzs(); 435 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 436 splx(s); 437 return (0); 438 } 439 440 /* 441 * Read/write zs serial port. 442 */ 443 int 444 zsread(dev, uio, flags) 445 dev_t dev; 446 struct uio *uio; 447 int flags; 448 { 449 register struct zs_chanstate *cs; 450 register struct zs_softc *zi; 451 register struct tty *tp; 452 int unit; 453 454 unit = ZS_UNIT(dev); 455 zi = zs_cd.cd_devs[unit >> 1]; 456 cs = &zi->zi_cs[unit & 1]; 457 tp = cs->cs_ttyp; 458 459 return(linesw[tp->t_line].l_read(tp, uio, flags)); 460 } 461 462 int 463 zswrite(dev, uio, flags) 464 dev_t dev; 465 struct uio *uio; 466 int flags; 467 { 468 register struct zs_chanstate *cs; 469 register struct zs_softc *zi; 470 register struct tty *tp; 471 int unit; 472 473 unit = ZS_UNIT(dev); 474 zi = zs_cd.cd_devs[unit >> 1]; 475 cs = &zi->zi_cs[unit & 1]; 476 tp = cs->cs_ttyp; 477 478 return(linesw[tp->t_line].l_write(tp, uio, flags)); 479 } 480 481 struct tty * 482 zstty(dev) 483 dev_t dev; 484 { 485 register struct zs_chanstate *cs; 486 register struct zs_softc *zi; 487 int unit; 488 489 unit = ZS_UNIT(dev); 490 zi = zs_cd.cd_devs[unit >> 1]; 491 cs = &zi->zi_cs[unit & 1]; 492 return(cs->cs_ttyp); 493 } 494 495 /* 496 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 497 * channels are kept in (A,B) pairs. 498 * 499 * Do just a little, then get out; set a software interrupt if more 500 * work is needed. 501 * 502 * We deliberately ignore the vectoring Zilog gives us, and match up 503 * only the number of `reset interrupt under service' operations, not 504 * the order. 505 */ 506 507 int 508 zshard(sr) 509 long sr; 510 { 511 register struct zs_chanstate *a; 512 #define b (a + 1) 513 register volatile struct zschan *zc; 514 register int rr3, intflags = 0, v, i; 515 516 do { 517 intflags &= ~4; 518 for(a = zslist; a != NULL; a = b->cs_next) { 519 rr3 = ZS_READ(a->cs_zc, 3); 520 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 521 intflags |= 4|2; 522 zc = a->cs_zc; 523 i = a->cs_rbput; 524 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 525 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 526 intflags |= 1; 527 } 528 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 529 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 530 intflags |= 1; 531 } 532 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 533 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 534 intflags |= 1; 535 } 536 a->cs_rbput = i; 537 } 538 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 539 intflags |= 4|2; 540 zc = b->cs_zc; 541 i = b->cs_rbput; 542 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 543 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 544 intflags |= 1; 545 } 546 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 547 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 548 intflags |= 1; 549 } 550 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 551 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 552 intflags |= 1; 553 } 554 b->cs_rbput = i; 555 } 556 } 557 } while(intflags & 4); 558 #undef b 559 560 if(intflags & 1) { 561 if(BASEPRI(sr)) { 562 spl1(); 563 zsshortcuts++; 564 return(zssoft(sr)); 565 } 566 else if(!cb_scheduled) { 567 cb_scheduled++; 568 add_sicallback((si_farg)zssoft, 0, 0); 569 } 570 } 571 return(intflags & 2); 572 } 573 574 static int 575 zsrint(cs, zc) 576 register struct zs_chanstate *cs; 577 register volatile struct zschan *zc; 578 { 579 register int c; 580 581 /* 582 * First read the status, because read of the received char 583 * destroy the status of this char. 584 */ 585 c = ZS_READ(zc, 1); 586 c |= (zc->zc_data << 8); 587 588 /* clear receive error & interrupt condition */ 589 zc->zc_csr = ZSWR0_RESET_ERRORS; 590 zc->zc_csr = ZSWR0_CLR_INTR; 591 592 return(ZRING_MAKE(ZRING_RINT, c)); 593 } 594 595 static int 596 zsxint(cs, zc) 597 register struct zs_chanstate *cs; 598 register volatile struct zschan *zc; 599 { 600 register int i = cs->cs_tbc; 601 602 if(i == 0) { 603 zc->zc_csr = ZSWR0_RESET_TXINT; 604 zc->zc_csr = ZSWR0_CLR_INTR; 605 return(ZRING_MAKE(ZRING_XINT, 0)); 606 } 607 cs->cs_tbc = i - 1; 608 zc->zc_data = *cs->cs_tba++; 609 zc->zc_csr = ZSWR0_CLR_INTR; 610 return (0); 611 } 612 613 static int 614 zssint(cs, zc) 615 register struct zs_chanstate *cs; 616 register volatile struct zschan *zc; 617 { 618 register int rr0; 619 620 rr0 = zc->zc_csr; 621 zc->zc_csr = ZSWR0_RESET_STATUS; 622 zc->zc_csr = ZSWR0_CLR_INTR; 623 /* 624 * The chip's hardware flow control is, as noted in zsreg.h, 625 * busted---if the DCD line goes low the chip shuts off the 626 * receiver (!). If we want hardware CTS flow control but do 627 * not have it, and carrier is now on, turn HFC on; if we have 628 * HFC now but carrier has gone low, turn it off. 629 */ 630 if(rr0 & ZSRR0_DCD) { 631 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 632 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 633 cs->cs_creg[3] |= ZSWR3_HFC; 634 ZS_WRITE(zc, 3, cs->cs_creg[3]); 635 } 636 } 637 else { 638 if (cs->cs_creg[3] & ZSWR3_HFC) { 639 cs->cs_creg[3] &= ~ZSWR3_HFC; 640 ZS_WRITE(zc, 3, cs->cs_creg[3]); 641 } 642 } 643 return(ZRING_MAKE(ZRING_SINT, rr0)); 644 } 645 646 /* 647 * Print out a ring or fifo overrun error message. 648 */ 649 static void 650 zsoverrun(unit, ptime, what) 651 int unit; 652 long *ptime; 653 char *what; 654 { 655 656 if(*ptime != time.tv_sec) { 657 *ptime = time.tv_sec; 658 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 659 (unit & 1) + 'a', what); 660 } 661 } 662 663 /* 664 * ZS software interrupt. Scan all channels for deferred interrupts. 665 */ 666 int 667 zssoft(sr) 668 long sr; 669 { 670 register struct zs_chanstate *cs; 671 register volatile struct zschan *zc; 672 register struct linesw *line; 673 register struct tty *tp; 674 register int get, n, c, cc, unit, s; 675 int retval = 0; 676 677 cb_scheduled = 0; 678 s = spltty(); 679 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 680 get = cs->cs_rbget; 681 again: 682 n = cs->cs_rbput; /* atomic */ 683 if(get == n) /* nothing more on this line */ 684 continue; 685 retval = 1; 686 unit = cs->cs_unit; /* set up to handle interrupts */ 687 zc = cs->cs_zc; 688 tp = cs->cs_ttyp; 689 line = &linesw[tp->t_line]; 690 /* 691 * Compute the number of interrupts in the receive ring. 692 * If the count is overlarge, we lost some events, and 693 * must advance to the first valid one. It may get 694 * overwritten if more data are arriving, but this is 695 * too expensive to check and gains nothing (we already 696 * lost out; all we can do at this point is trade one 697 * kind of loss for another). 698 */ 699 n -= get; 700 if(n > ZLRB_RING_SIZE) { 701 zsoverrun(unit, &cs->cs_rotime, "ring"); 702 get += n - ZLRB_RING_SIZE; 703 n = ZLRB_RING_SIZE; 704 } 705 while(--n >= 0) { 706 /* race to keep ahead of incoming interrupts */ 707 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 708 switch (ZRING_TYPE(c)) { 709 710 case ZRING_RINT: 711 c = ZRING_VALUE(c); 712 if(c & ZSRR1_DO) 713 zsoverrun(unit, &cs->cs_fotime, "fifo"); 714 cc = c >> 8; 715 if(c & ZSRR1_FE) 716 cc |= TTY_FE; 717 if(c & ZSRR1_PE) 718 cc |= TTY_PE; 719 line->l_rint(cc, tp); 720 break; 721 722 case ZRING_XINT: 723 /* 724 * Transmit done: change registers and resume, 725 * or clear BUSY. 726 */ 727 if(cs->cs_heldchange) { 728 int sps; 729 730 sps = splzs(); 731 c = zc->zc_csr; 732 if((c & ZSRR0_DCD) == 0) 733 cs->cs_preg[3] &= ~ZSWR3_HFC; 734 bcopy((caddr_t)cs->cs_preg, 735 (caddr_t)cs->cs_creg, 16); 736 zs_loadchannelregs(zc, cs->cs_creg); 737 splx(sps); 738 cs->cs_heldchange = 0; 739 if(cs->cs_heldtbc 740 && (tp->t_state & TS_TTSTOP) == 0) { 741 cs->cs_tbc = cs->cs_heldtbc - 1; 742 zc->zc_data = *cs->cs_tba++; 743 goto again; 744 } 745 } 746 tp->t_state &= ~TS_BUSY; 747 if(tp->t_state & TS_FLUSH) 748 tp->t_state &= ~TS_FLUSH; 749 else ndflush(&tp->t_outq,cs->cs_tba 750 - (caddr_t)tp->t_outq.c_cf); 751 line->l_start(tp); 752 break; 753 754 case ZRING_SINT: 755 /* 756 * Status line change. HFC bit is run in 757 * hardware interrupt, to avoid locking 758 * at splzs here. 759 */ 760 c = ZRING_VALUE(c); 761 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 762 cc = (c & ZSRR0_DCD) != 0; 763 if(line->l_modem(tp, cc) == 0) 764 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 765 cc ? DMBIS : DMBIC); 766 } 767 cs->cs_rr0 = c; 768 break; 769 770 default: 771 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 772 unit >> 1, (unit & 1) + 'a', c); 773 break; 774 } 775 } 776 cs->cs_rbget = get; 777 goto again; 778 } 779 splx(s); 780 return (retval); 781 } 782 783 int 784 zsioctl(dev, cmd, data, flag, p) 785 dev_t dev; 786 u_long cmd; 787 caddr_t data; 788 int flag; 789 struct proc *p; 790 { 791 int unit = ZS_UNIT(dev); 792 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 793 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 794 register int error, s; 795 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 796 797 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 798 if(error >= 0) 799 return(error); 800 error = ttioctl(tp, cmd, data, flag, p); 801 if(error >= 0) 802 return (error); 803 804 switch (cmd) { 805 case TIOCSBRK: 806 s = splzs(); 807 cs->cs_preg[5] |= ZSWR5_BREAK; 808 cs->cs_creg[5] |= ZSWR5_BREAK; 809 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 810 splx(s); 811 break; 812 case TIOCCBRK: 813 s = splzs(); 814 cs->cs_preg[5] &= ~ZSWR5_BREAK; 815 cs->cs_creg[5] &= ~ZSWR5_BREAK; 816 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 817 splx(s); 818 break; 819 case TIOCGFLAGS: { 820 int bits = 0; 821 822 if(cs->cs_softcar) 823 bits |= TIOCFLAG_SOFTCAR; 824 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 825 bits |= TIOCFLAG_CLOCAL; 826 if(cs->cs_creg[3] & ZSWR3_HFC) 827 bits |= TIOCFLAG_CRTSCTS; 828 *(int *)data = bits; 829 break; 830 } 831 case TIOCSFLAGS: { 832 int userbits = 0; 833 834 error = suser(p->p_ucred, &p->p_acflag); 835 if(error != 0) 836 return (EPERM); 837 838 userbits = *(int *)data; 839 840 /* 841 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 842 # defaulting to software flow control. 843 */ 844 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 845 return(EINVAL); 846 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 847 return(ENODEV); 848 849 s = splzs(); 850 if((userbits & TIOCFLAG_SOFTCAR)) { 851 cs->cs_softcar = 1; /* turn on softcar */ 852 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 853 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 854 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 855 } 856 else if(userbits & TIOCFLAG_CLOCAL) { 857 cs->cs_softcar = 0; /* turn off softcar */ 858 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 859 cs->cs_creg[15] |= ZSWR15_DCD_IE; 860 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 861 tp->t_termios.c_cflag |= CLOCAL; 862 } 863 if(userbits & TIOCFLAG_CRTSCTS) { 864 cs->cs_preg[15] |= ZSWR15_CTS_IE; 865 cs->cs_creg[15] |= ZSWR15_CTS_IE; 866 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 867 cs->cs_preg[3] |= ZSWR3_HFC; 868 cs->cs_creg[3] |= ZSWR3_HFC; 869 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 870 tp->t_termios.c_cflag |= CRTSCTS; 871 } 872 else { 873 /* no mdmbuf, so we must want software flow control */ 874 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 875 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 876 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 877 cs->cs_preg[3] &= ~ZSWR3_HFC; 878 cs->cs_creg[3] &= ~ZSWR3_HFC; 879 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 880 tp->t_termios.c_cflag &= ~CRTSCTS; 881 } 882 splx(s); 883 break; 884 } 885 case TIOCSDTR: 886 zs_modem(cs, ZSWR5_DTR, DMBIS); 887 break; 888 case TIOCCDTR: 889 zs_modem(cs, ZSWR5_DTR, DMBIC); 890 break; 891 case TIOCMGET: 892 zs_modem(cs, 0, DMGET); 893 break; 894 case TIOCMSET: 895 case TIOCMBIS: 896 case TIOCMBIC: 897 default: 898 return (ENOTTY); 899 } 900 return (0); 901 } 902 903 /* 904 * Start or restart transmission. 905 */ 906 static void 907 zsstart(tp) 908 register struct tty *tp; 909 { 910 register struct zs_chanstate *cs; 911 register int s, nch; 912 int unit = ZS_UNIT(tp->t_dev); 913 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 914 915 cs = &zi->zi_cs[unit & 1]; 916 s = spltty(); 917 918 /* 919 * If currently active or delaying, no need to do anything. 920 */ 921 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 922 goto out; 923 924 /* 925 * If there are sleepers, and output has drained below low 926 * water mark, awaken. 927 */ 928 if(tp->t_outq.c_cc <= tp->t_lowat) { 929 if(tp->t_state & TS_ASLEEP) { 930 tp->t_state &= ~TS_ASLEEP; 931 wakeup((caddr_t)&tp->t_outq); 932 } 933 selwakeup(&tp->t_wsel); 934 } 935 936 nch = ndqb(&tp->t_outq, 0); /* XXX */ 937 if(nch) { 938 register char *p = tp->t_outq.c_cf; 939 940 /* mark busy, enable tx done interrupts, & send first byte */ 941 tp->t_state |= TS_BUSY; 942 (void) splzs(); 943 cs->cs_preg[1] |= ZSWR1_TIE; 944 cs->cs_creg[1] |= ZSWR1_TIE; 945 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 946 cs->cs_zc->zc_data = *p; 947 cs->cs_tba = p + 1; 948 cs->cs_tbc = nch - 1; 949 } else { 950 /* 951 * Nothing to send, turn off transmit done interrupts. 952 * This is useful if something is doing polled output. 953 */ 954 (void) splzs(); 955 cs->cs_preg[1] &= ~ZSWR1_TIE; 956 cs->cs_creg[1] &= ~ZSWR1_TIE; 957 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 958 } 959 out: 960 splx(s); 961 } 962 963 /* 964 * Stop output, e.g., for ^S or output flush. 965 */ 966 void 967 zsstop(tp, flag) 968 register struct tty *tp; 969 int flag; 970 { 971 register struct zs_chanstate *cs; 972 register int s, unit = ZS_UNIT(tp->t_dev); 973 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 974 975 cs = &zi->zi_cs[unit & 1]; 976 s = splzs(); 977 if(tp->t_state & TS_BUSY) { 978 /* 979 * Device is transmitting; must stop it. 980 */ 981 cs->cs_tbc = 0; 982 if ((tp->t_state & TS_TTSTOP) == 0) 983 tp->t_state |= TS_FLUSH; 984 } 985 splx(s); 986 } 987 988 /* 989 * Set ZS tty parameters from termios. 990 * 991 * This routine makes use of the fact that only registers 992 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 993 */ 994 static int 995 zsparam(tp, t) 996 register struct tty *tp; 997 register struct termios *t; 998 { 999 int unit = ZS_UNIT(tp->t_dev); 1000 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1001 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1002 int cdiv, clkm, brgm, tcon; 1003 register int tmp, tmp5, cflag, s; 1004 1005 tmp = t->c_ospeed; 1006 tmp5 = t->c_ispeed; 1007 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1008 return(EINVAL); 1009 if(tmp == 0) { 1010 /* stty 0 => drop DTR and RTS */ 1011 zs_modem(cs, 0, DMSET); 1012 return(0); 1013 } 1014 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1015 if (tmp < 0) 1016 return(EINVAL); 1017 tp->t_ispeed = tp->t_ospeed = tmp; 1018 1019 cflag = tp->t_cflag = t->c_cflag; 1020 if (cflag & CSTOPB) 1021 cdiv |= ZSWR4_TWOSB; 1022 else 1023 cdiv |= ZSWR4_ONESB; 1024 if (!(cflag & PARODD)) 1025 cdiv |= ZSWR4_EVENP; 1026 if (cflag & PARENB) 1027 cdiv |= ZSWR4_PARENB; 1028 1029 switch(cflag & CSIZE) { 1030 case CS5: 1031 tmp = ZSWR3_RX_5; 1032 tmp5 = ZSWR5_TX_5; 1033 break; 1034 case CS6: 1035 tmp = ZSWR3_RX_6; 1036 tmp5 = ZSWR5_TX_6; 1037 break; 1038 case CS7: 1039 tmp = ZSWR3_RX_7; 1040 tmp5 = ZSWR5_TX_7; 1041 break; 1042 case CS8: 1043 default: 1044 tmp = ZSWR3_RX_8; 1045 tmp5 = ZSWR5_TX_8; 1046 break; 1047 } 1048 tmp |= ZSWR3_RX_ENABLE; 1049 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1050 1051 /* 1052 * Block interrupts so that state will not 1053 * be altered until we are done setting it up. 1054 */ 1055 s = splzs(); 1056 cs->cs_preg[4] = cdiv; 1057 cs->cs_preg[11] = clkm; 1058 cs->cs_preg[12] = tcon; 1059 cs->cs_preg[13] = tcon >> 8; 1060 cs->cs_preg[14] = brgm; 1061 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1062 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1063 cs->cs_preg[10] = ZSWR10_NRZ; 1064 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1065 1066 /* 1067 * Output hardware flow control on the chip is horrendous: if 1068 * carrier detect drops, the receiver is disabled. Hence we 1069 * can only do this when the carrier is on. 1070 */ 1071 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1072 tmp |= ZSWR3_HFC; 1073 cs->cs_preg[3] = tmp; 1074 cs->cs_preg[5] = tmp5; 1075 1076 /* 1077 * If nothing is being transmitted, set up new current values, 1078 * else mark them as pending. 1079 */ 1080 if(cs->cs_heldchange == 0) { 1081 if (cs->cs_ttyp->t_state & TS_BUSY) { 1082 cs->cs_heldtbc = cs->cs_tbc; 1083 cs->cs_tbc = 0; 1084 cs->cs_heldchange = 1; 1085 } else { 1086 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1087 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1088 } 1089 } 1090 splx(s); 1091 return (0); 1092 } 1093 1094 /* 1095 * search for the best matching baudrate 1096 */ 1097 static int 1098 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1099 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1100 { 1101 int bestdiff, bestbps, source; 1102 1103 bestdiff = bestbps = 0; 1104 unit = (unit & 1) << 2; 1105 for (source = 0; source < 4; ++source) { 1106 long freq = zs_frequencies[unit + source]; 1107 int diff, bps, div, clkm, brgm, tcon; 1108 1109 bps = div = clkm = brgm = tcon = 0; 1110 switch (source) { 1111 case 0: /* BRgen, PCLK */ 1112 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1113 break; 1114 case 1: /* BRgen, RTxC */ 1115 brgm = ZSWR14_BAUD_ENA; 1116 break; 1117 case 2: /* RTxC */ 1118 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1119 break; 1120 case 3: /* TRxC */ 1121 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1122 break; 1123 } 1124 switch (source) { 1125 case 0: 1126 case 1: 1127 div = ZSWR4_CLK_X16; 1128 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1129 tcon = BPS_TO_TCONST(freq, wanted); 1130 if (tcon < 0) 1131 tcon = 0; 1132 bps = TCONST_TO_BPS(freq, tcon); 1133 break; 1134 case 2: 1135 case 3: 1136 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1137 int b2 = freq / 32, d2 = abs(b2 - wanted); 1138 int b3 = freq / 64, d3 = abs(b3 - wanted); 1139 1140 if (d1 < d2 && d1 < d3) { 1141 div = ZSWR4_CLK_X16; 1142 bps = b1; 1143 } else if (d2 < d3 && d2 < d1) { 1144 div = ZSWR4_CLK_X32; 1145 bps = b2; 1146 } else { 1147 div = ZSWR4_CLK_X64; 1148 bps = b3; 1149 } 1150 brgm = tcon = 0; 1151 break; 1152 } 1153 } 1154 diff = abs(bps - wanted); 1155 if (!source || diff < bestdiff) { 1156 *divisor = div; 1157 *clockmode = clkm; 1158 *brgenmode = brgm; 1159 *timeconst = tcon; 1160 bestbps = bps; 1161 bestdiff = diff; 1162 if (diff == 0) 1163 break; 1164 } 1165 } 1166 /* Allow deviations upto 5% */ 1167 if (20 * bestdiff > wanted) 1168 return -1; 1169 return bestbps; 1170 } 1171 1172 /* 1173 * Raise or lower modem control (DTR/RTS) signals. If a character is 1174 * in transmission, the change is deferred. 1175 */ 1176 static int 1177 zs_modem(cs, bits, how) 1178 struct zs_chanstate *cs; 1179 int bits, how; 1180 { 1181 int s, mbits; 1182 1183 bits &= ZSWR5_DTR | ZSWR5_RTS; 1184 1185 s = splzs(); 1186 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1187 1188 switch(how) { 1189 case DMSET: 1190 mbits = bits; 1191 break; 1192 case DMBIS: 1193 mbits |= bits; 1194 break; 1195 case DMBIC: 1196 mbits &= ~bits; 1197 break; 1198 case DMGET: 1199 splx(s); 1200 return(mbits); 1201 } 1202 1203 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1204 if(cs->cs_heldchange == 0) { 1205 if(cs->cs_ttyp->t_state & TS_BUSY) { 1206 cs->cs_heldtbc = cs->cs_tbc; 1207 cs->cs_tbc = 0; 1208 cs->cs_heldchange = 1; 1209 } 1210 else { 1211 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1212 } 1213 } 1214 splx(s); 1215 return(0); 1216 } 1217 1218 /* 1219 * Write the given register set to the given zs channel in the proper order. 1220 * The channel must not be transmitting at the time. The receiver will 1221 * be disabled for the time it takes to write all the registers. 1222 */ 1223 static void 1224 zs_loadchannelregs(zc, reg) 1225 volatile struct zschan *zc; 1226 u_char *reg; 1227 { 1228 int i; 1229 1230 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1231 i = zc->zc_data; /* drain fifo */ 1232 i = zc->zc_data; 1233 i = zc->zc_data; 1234 ZS_WRITE(zc, 4, reg[4]); 1235 ZS_WRITE(zc, 10, reg[10]); 1236 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1237 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1238 ZS_WRITE(zc, 1, reg[1]); 1239 ZS_WRITE(zc, 9, reg[9]); 1240 ZS_WRITE(zc, 11, reg[11]); 1241 ZS_WRITE(zc, 12, reg[12]); 1242 ZS_WRITE(zc, 13, reg[13]); 1243 ZS_WRITE(zc, 14, reg[14]); 1244 ZS_WRITE(zc, 15, reg[15]); 1245 ZS_WRITE(zc, 3, reg[3]); 1246 ZS_WRITE(zc, 5, reg[5]); 1247 } 1248 #endif /* NZS > 1 */ 1249