1 /* $NetBSD: zs.c,v 1.24 1996/11/10 21:52:37 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49 /* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/proc.h> 59 #include <sys/device.h> 60 #include <sys/conf.h> 61 #include <sys/file.h> 62 #include <sys/ioctl.h> 63 #include <sys/malloc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/kernel.h> 67 #include <sys/syslog.h> 68 69 #include <machine/cpu.h> 70 #include <machine/iomap.h> 71 #include <machine/scu.h> 72 #include <machine/mfp.h> 73 #include <atari/dev/ym2149reg.h> 74 75 #include <dev/ic/z8530reg.h> 76 #include <atari/dev/zsvar.h> 77 #include "zs.h" 78 #if NZS > 1 79 #error "This driver supports only 1 85C30!" 80 #endif 81 82 #if NZS > 0 83 84 #define PCLK (8053976) /* PCLK pin input clock rate */ 85 #define PCLK_HD (14745600) /* PCLK on Hades pin input clock rate */ 86 87 #define splzs spl5 88 89 /* 90 * Software state per found chip. 91 */ 92 struct zs_softc { 93 struct device zi_dev; /* base device */ 94 volatile struct zsdevice *zi_zs; /* chip registers */ 95 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 96 }; 97 98 static u_char cb_scheduled = 0; /* Already asked for callback? */ 99 /* 100 * Define the registers for a closed port 101 */ 102 static u_char zs_init_regs[16] = { 103 /* 0 */ 0, 104 /* 1 */ 0, 105 /* 2 */ 0x60, 106 /* 3 */ 0, 107 /* 4 */ 0, 108 /* 5 */ 0, 109 /* 6 */ 0, 110 /* 7 */ 0, 111 /* 8 */ 0, 112 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 113 /* 10 */ ZSWR10_NRZ, 114 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115 /* 12 */ 0, 116 /* 13 */ 0, 117 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 118 /* 15 */ 0 119 }; 120 121 /* 122 * Define the machine dependant clock frequencies 123 * If BRgen feeds sender/receiver we always use a 124 * divisor 16, therefor the division by 16 can as 125 * well be done here. 126 */ 127 static u_long zs_freqs_tt[] = { 128 /* 129 * Atari TT, RTxCB is generated by TT-MFP timer C, 130 * which is set to 307.2KHz during initialisation 131 * and never changed afterwards. 132 */ 133 PCLK/16, /* BRgen, PCLK, divisor 16 */ 134 229500, /* BRgen, RTxCA, divisor 16 */ 135 3672000, /* RTxCA, from PCLK4 */ 136 0, /* TRxCA, external */ 137 138 PCLK/16, /* BRgen, PCLK, divisor 16 */ 139 19200, /* BRgen, RTxCB, divisor 16 */ 140 307200, /* RTxCB, from TT-MFP TCO */ 141 2457600 /* TRxCB, from BCLK */ 142 }; 143 144 static u_long zs_freqs_falcon[] = { 145 /* 146 * Atari Falcon, XXX no specs available, this might be wrong 147 */ 148 PCLK/16, /* BRgen, PCLK, divisor 16 */ 149 229500, /* BRgen, RTxCA, divisor 16 */ 150 3672000, /* RTxCA, ??? */ 151 0, /* TRxCA, external */ 152 153 PCLK/16, /* BRgen, PCLK, divisor 16 */ 154 229500, /* BRgen, RTxCB, divisor 16 */ 155 3672000, /* RTxCB, ??? */ 156 2457600 /* TRxCB, ??? */ 157 }; 158 159 static u_long zs_freqs_hades[] = { 160 /* 161 * XXX: Channel-A unchecked!!!!! 162 */ 163 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 164 229500, /* BRgen, RTxCA, divisor 16 */ 165 3672000, /* RTxCA, from PCLK4 */ 166 0, /* TRxCA, external */ 167 168 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 169 235550, /* BRgen, RTxCB, divisor 16 */ 170 3768800, /* RTxCB, 3.7688MHz */ 171 3768800 /* TRxCB, 3.7688MHz */ 172 }; 173 174 static u_long zs_freqs_generic[] = { 175 /* 176 * other machines, assume only PCLK is available 177 */ 178 PCLK/16, /* BRgen, PCLK, divisor 16 */ 179 0, /* BRgen, RTxCA, divisor 16 */ 180 0, /* RTxCA, unknown */ 181 0, /* TRxCA, unknown */ 182 183 PCLK/16, /* BRgen, PCLK, divisor 16 */ 184 0, /* BRgen, RTxCB, divisor 16 */ 185 0, /* RTxCB, unknown */ 186 0 /* TRxCB, unknown */ 187 }; 188 static u_long *zs_frequencies; 189 190 /* Definition of the driver for autoconfig. */ 191 static int zsmatch __P((struct device *, void *, void *)); 192 static void zsattach __P((struct device *, struct device *, void *)); 193 194 struct cfattach zs_ca = { 195 sizeof(struct zs_softc), zsmatch, zsattach 196 }; 197 198 struct cfdriver zs_cd = { 199 NULL, "zs", DV_TTY, NULL, 0 200 }; 201 202 /* {b,c}devsw[] function prototypes */ 203 dev_type_open(zsopen); 204 dev_type_close(zsclose); 205 dev_type_read(zsread); 206 dev_type_write(zswrite); 207 dev_type_ioctl(zsioctl); 208 dev_type_tty(zstty); 209 210 /* Interrupt handlers. */ 211 int zshard __P((long)); 212 static int zssoft __P((long)); 213 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 214 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 215 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 216 217 static struct zs_chanstate *zslist; 218 219 /* Routines called from other code. */ 220 static void zsstart __P((struct tty *)); 221 void zsstop __P((struct tty *, int)); 222 223 /* Routines purely local to this driver. */ 224 static void zsoverrun __P((int, long *, char *)); 225 static int zsparam __P((struct tty *, struct termios *)); 226 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 227 static int zs_modem __P((struct zs_chanstate *, int, int)); 228 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 229 230 static int zsshortcuts; /* number of "shortcut" software interrupts */ 231 232 static int 233 zsmatch(pdp, match, auxp) 234 struct device *pdp; 235 void *match, *auxp; 236 { 237 struct cfdata *cfp = match; 238 239 if(strcmp("zs", auxp) || cfp->cf_unit != 0) 240 return(0); 241 return(1); 242 } 243 244 /* 245 * Attach a found zs. 246 */ 247 static void 248 zsattach(parent, dev, aux) 249 struct device *parent; 250 struct device *dev; 251 void *aux; 252 { 253 register struct zs_softc *zi; 254 register struct zs_chanstate *cs; 255 register volatile struct zsdevice *addr; 256 char tmp; 257 258 addr = (struct zsdevice *)AD_SCC; 259 zi = (struct zs_softc *)dev; 260 zi->zi_zs = addr; 261 cs = zi->zi_cs; 262 263 /* 264 * Get the command register into a known state. 265 */ 266 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 267 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 268 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 269 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 270 271 /* 272 * Do a hardware reset. 273 */ 274 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 275 delay(50000); /*enough ? */ 276 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 277 278 /* 279 * Initialize both channels 280 */ 281 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 282 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 283 284 if(machineid & ATARI_TT) { 285 /* 286 * ininitialise TT-MFP timer C: 307200Hz 287 * timer C and D share one control register: 288 * bits 0-2 control timer D 289 * bits 4-6 control timer C 290 */ 291 int cr = MFP2->mf_tcdcr & 7; 292 MFP2->mf_tcdcr = cr; /* stop timer C */ 293 MFP2->mf_tcdr = 1; /* counter 1 */ 294 cr |= T_Q004 << 4; /* divisor 4 */ 295 MFP2->mf_tcdcr = cr; /* start timer C */ 296 /* 297 * enable scc related interrupts 298 */ 299 SCU->sys_mask |= SCU_SCC; 300 301 zs_frequencies = zs_freqs_tt; 302 } else if (machineid & ATARI_FALCON) { 303 zs_frequencies = zs_freqs_falcon; 304 } else if (machineid & ATARI_HADES) { 305 zs_frequencies = zs_freqs_hades; 306 } else { 307 zs_frequencies = zs_freqs_generic; 308 } 309 310 /* link into interrupt list with order (A,B) (B=A+1) */ 311 cs[0].cs_next = &cs[1]; 312 cs[1].cs_next = zslist; 313 zslist = cs; 314 315 cs->cs_unit = 0; 316 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 317 cs++; 318 cs->cs_unit = 1; 319 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 320 321 printf(": serial2 on channel a and modem2 on channel b\n"); 322 } 323 324 /* 325 * Open a zs serial port. 326 */ 327 int 328 zsopen(dev, flags, mode, p) 329 dev_t dev; 330 int flags; 331 int mode; 332 struct proc *p; 333 { 334 register struct tty *tp; 335 register struct zs_chanstate *cs; 336 struct zs_softc *zi; 337 int unit = ZS_UNIT(dev); 338 int zs = unit >> 1; 339 int error, s; 340 341 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 342 return (ENXIO); 343 cs = &zi->zi_cs[unit & 1]; 344 345 /* 346 * When port A (ser02) is selected on the TT, make sure 347 * the port is enabled. 348 */ 349 if((machineid & ATARI_TT) && !(unit & 1)) 350 ym2149_ser2_select(); 351 352 if (cs->cs_rbuf == NULL) { 353 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 354 M_WAITOK); 355 } 356 357 tp = cs->cs_ttyp; 358 if(tp == NULL) { 359 cs->cs_ttyp = tp = ttymalloc(); 360 tty_attach(tp); 361 tp->t_dev = dev; 362 tp->t_oproc = zsstart; 363 tp->t_param = zsparam; 364 } 365 366 s = spltty(); 367 if((tp->t_state & TS_ISOPEN) == 0) { 368 ttychars(tp); 369 if(tp->t_ispeed == 0) { 370 tp->t_iflag = TTYDEF_IFLAG; 371 tp->t_oflag = TTYDEF_OFLAG; 372 tp->t_cflag = TTYDEF_CFLAG; 373 tp->t_lflag = TTYDEF_LFLAG; 374 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 375 } 376 (void)zsparam(tp, &tp->t_termios); 377 ttsetwater(tp); 378 } 379 else if(tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) { 380 splx(s); 381 return (EBUSY); 382 } 383 error = 0; 384 for(;;) { 385 /* loop, turning on the device, until carrier present */ 386 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 387 388 /* May never get a status intr. if DCD already on. -gwr */ 389 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 390 tp->t_state |= TS_CARR_ON; 391 if(cs->cs_softcar) 392 tp->t_state |= TS_CARR_ON; 393 if(flags & O_NONBLOCK || tp->t_cflag & CLOCAL || 394 tp->t_state & TS_CARR_ON) 395 break; 396 tp->t_state |= TS_WOPEN; 397 if((error = ttysleep(tp, (caddr_t)&tp->t_rawq, TTIPRI | PCATCH, 398 ttopen, 0)) != 0) { 399 if(!(tp->t_state & TS_ISOPEN)) { 400 zs_modem(cs, 0, DMSET); 401 tp->t_state &= ~TS_WOPEN; 402 ttwakeup(tp); 403 } 404 splx(s); 405 return error; 406 } 407 } 408 splx(s); 409 if(error == 0) 410 error = linesw[tp->t_line].l_open(dev, tp); 411 if(error) 412 zs_modem(cs, 0, DMSET); 413 return(error); 414 } 415 416 /* 417 * Close a zs serial port. 418 */ 419 int 420 zsclose(dev, flags, mode, p) 421 dev_t dev; 422 int flags; 423 int mode; 424 struct proc *p; 425 { 426 register struct zs_chanstate *cs; 427 register struct tty *tp; 428 struct zs_softc *zi; 429 int unit = ZS_UNIT(dev); 430 int s; 431 432 zi = zs_cd.cd_devs[unit >> 1]; 433 cs = &zi->zi_cs[unit & 1]; 434 tp = cs->cs_ttyp; 435 linesw[tp->t_line].l_close(tp, flags); 436 if(tp->t_cflag & HUPCL || tp->t_state & TS_WOPEN || 437 (tp->t_state & TS_ISOPEN) == 0) { 438 zs_modem(cs, 0, DMSET); 439 /* hold low for 1 second */ 440 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 441 } 442 if(cs->cs_creg[5] & ZSWR5_BREAK) { 443 s = splzs(); 444 cs->cs_preg[5] &= ~ZSWR5_BREAK; 445 cs->cs_creg[5] &= ~ZSWR5_BREAK; 446 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 447 splx(s); 448 } 449 ttyclose(tp); 450 451 /* 452 * Drop all lines and cancel interrupts 453 */ 454 s = splzs(); 455 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 456 splx(s); 457 return (0); 458 } 459 460 /* 461 * Read/write zs serial port. 462 */ 463 int 464 zsread(dev, uio, flags) 465 dev_t dev; 466 struct uio *uio; 467 int flags; 468 { 469 register struct zs_chanstate *cs; 470 register struct zs_softc *zi; 471 register struct tty *tp; 472 int unit; 473 474 unit = ZS_UNIT(dev); 475 zi = zs_cd.cd_devs[unit >> 1]; 476 cs = &zi->zi_cs[unit & 1]; 477 tp = cs->cs_ttyp; 478 479 return(linesw[tp->t_line].l_read(tp, uio, flags)); 480 } 481 482 int 483 zswrite(dev, uio, flags) 484 dev_t dev; 485 struct uio *uio; 486 int flags; 487 { 488 register struct zs_chanstate *cs; 489 register struct zs_softc *zi; 490 register struct tty *tp; 491 int unit; 492 493 unit = ZS_UNIT(dev); 494 zi = zs_cd.cd_devs[unit >> 1]; 495 cs = &zi->zi_cs[unit & 1]; 496 tp = cs->cs_ttyp; 497 498 return(linesw[tp->t_line].l_write(tp, uio, flags)); 499 } 500 501 struct tty * 502 zstty(dev) 503 dev_t dev; 504 { 505 register struct zs_chanstate *cs; 506 register struct zs_softc *zi; 507 int unit; 508 509 unit = ZS_UNIT(dev); 510 zi = zs_cd.cd_devs[unit >> 1]; 511 cs = &zi->zi_cs[unit & 1]; 512 return(cs->cs_ttyp); 513 } 514 515 /* 516 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 517 * channels are kept in (A,B) pairs. 518 * 519 * Do just a little, then get out; set a software interrupt if more 520 * work is needed. 521 * 522 * We deliberately ignore the vectoring Zilog gives us, and match up 523 * only the number of `reset interrupt under service' operations, not 524 * the order. 525 */ 526 527 int 528 zshard(sr) 529 long sr; 530 { 531 register struct zs_chanstate *a; 532 #define b (a + 1) 533 register volatile struct zschan *zc; 534 register int rr3, intflags = 0, v, i; 535 536 do { 537 intflags &= ~4; 538 for(a = zslist; a != NULL; a = b->cs_next) { 539 rr3 = ZS_READ(a->cs_zc, 3); 540 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 541 intflags |= 4|2; 542 zc = a->cs_zc; 543 i = a->cs_rbput; 544 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 545 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 546 intflags |= 1; 547 } 548 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 549 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 550 intflags |= 1; 551 } 552 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 553 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 554 intflags |= 1; 555 } 556 a->cs_rbput = i; 557 } 558 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 559 intflags |= 4|2; 560 zc = b->cs_zc; 561 i = b->cs_rbput; 562 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 563 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 564 intflags |= 1; 565 } 566 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 567 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 568 intflags |= 1; 569 } 570 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 571 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 572 intflags |= 1; 573 } 574 b->cs_rbput = i; 575 } 576 } 577 } while(intflags & 4); 578 #undef b 579 580 if(intflags & 1) { 581 if(BASEPRI(sr)) { 582 spl1(); 583 zsshortcuts++; 584 return(zssoft(sr)); 585 } 586 else if(!cb_scheduled) { 587 cb_scheduled++; 588 add_sicallback((si_farg)zssoft, 0, 0); 589 } 590 } 591 return(intflags & 2); 592 } 593 594 static int 595 zsrint(cs, zc) 596 register struct zs_chanstate *cs; 597 register volatile struct zschan *zc; 598 { 599 register int c; 600 601 /* 602 * First read the status, because read of the received char 603 * destroy the status of this char. 604 */ 605 c = ZS_READ(zc, 1); 606 c |= (zc->zc_data << 8); 607 608 /* clear receive error & interrupt condition */ 609 zc->zc_csr = ZSWR0_RESET_ERRORS; 610 zc->zc_csr = ZSWR0_CLR_INTR; 611 612 return(ZRING_MAKE(ZRING_RINT, c)); 613 } 614 615 static int 616 zsxint(cs, zc) 617 register struct zs_chanstate *cs; 618 register volatile struct zschan *zc; 619 { 620 register int i = cs->cs_tbc; 621 622 if(i == 0) { 623 zc->zc_csr = ZSWR0_RESET_TXINT; 624 zc->zc_csr = ZSWR0_CLR_INTR; 625 return(ZRING_MAKE(ZRING_XINT, 0)); 626 } 627 cs->cs_tbc = i - 1; 628 zc->zc_data = *cs->cs_tba++; 629 zc->zc_csr = ZSWR0_CLR_INTR; 630 return (0); 631 } 632 633 static int 634 zssint(cs, zc) 635 register struct zs_chanstate *cs; 636 register volatile struct zschan *zc; 637 { 638 register int rr0; 639 640 rr0 = zc->zc_csr; 641 zc->zc_csr = ZSWR0_RESET_STATUS; 642 zc->zc_csr = ZSWR0_CLR_INTR; 643 /* 644 * The chip's hardware flow control is, as noted in zsreg.h, 645 * busted---if the DCD line goes low the chip shuts off the 646 * receiver (!). If we want hardware CTS flow control but do 647 * not have it, and carrier is now on, turn HFC on; if we have 648 * HFC now but carrier has gone low, turn it off. 649 */ 650 if(rr0 & ZSRR0_DCD) { 651 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 652 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 653 cs->cs_creg[3] |= ZSWR3_HFC; 654 ZS_WRITE(zc, 3, cs->cs_creg[3]); 655 } 656 } 657 else { 658 if (cs->cs_creg[3] & ZSWR3_HFC) { 659 cs->cs_creg[3] &= ~ZSWR3_HFC; 660 ZS_WRITE(zc, 3, cs->cs_creg[3]); 661 } 662 } 663 return(ZRING_MAKE(ZRING_SINT, rr0)); 664 } 665 666 /* 667 * Print out a ring or fifo overrun error message. 668 */ 669 static void 670 zsoverrun(unit, ptime, what) 671 int unit; 672 long *ptime; 673 char *what; 674 { 675 676 if(*ptime != time.tv_sec) { 677 *ptime = time.tv_sec; 678 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 679 (unit & 1) + 'a', what); 680 } 681 } 682 683 /* 684 * ZS software interrupt. Scan all channels for deferred interrupts. 685 */ 686 int 687 zssoft(sr) 688 long sr; 689 { 690 register struct zs_chanstate *cs; 691 register volatile struct zschan *zc; 692 register struct linesw *line; 693 register struct tty *tp; 694 register int get, n, c, cc, unit, s; 695 int retval = 0; 696 697 cb_scheduled = 0; 698 s = spltty(); 699 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 700 get = cs->cs_rbget; 701 again: 702 n = cs->cs_rbput; /* atomic */ 703 if(get == n) /* nothing more on this line */ 704 continue; 705 retval = 1; 706 unit = cs->cs_unit; /* set up to handle interrupts */ 707 zc = cs->cs_zc; 708 tp = cs->cs_ttyp; 709 line = &linesw[tp->t_line]; 710 /* 711 * Compute the number of interrupts in the receive ring. 712 * If the count is overlarge, we lost some events, and 713 * must advance to the first valid one. It may get 714 * overwritten if more data are arriving, but this is 715 * too expensive to check and gains nothing (we already 716 * lost out; all we can do at this point is trade one 717 * kind of loss for another). 718 */ 719 n -= get; 720 if(n > ZLRB_RING_SIZE) { 721 zsoverrun(unit, &cs->cs_rotime, "ring"); 722 get += n - ZLRB_RING_SIZE; 723 n = ZLRB_RING_SIZE; 724 } 725 while(--n >= 0) { 726 /* race to keep ahead of incoming interrupts */ 727 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 728 switch (ZRING_TYPE(c)) { 729 730 case ZRING_RINT: 731 c = ZRING_VALUE(c); 732 if(c & ZSRR1_DO) 733 zsoverrun(unit, &cs->cs_fotime, "fifo"); 734 cc = c >> 8; 735 if(c & ZSRR1_FE) 736 cc |= TTY_FE; 737 if(c & ZSRR1_PE) 738 cc |= TTY_PE; 739 line->l_rint(cc, tp); 740 break; 741 742 case ZRING_XINT: 743 /* 744 * Transmit done: change registers and resume, 745 * or clear BUSY. 746 */ 747 if(cs->cs_heldchange) { 748 int sps; 749 750 sps = splzs(); 751 c = zc->zc_csr; 752 if((c & ZSRR0_DCD) == 0) 753 cs->cs_preg[3] &= ~ZSWR3_HFC; 754 bcopy((caddr_t)cs->cs_preg, 755 (caddr_t)cs->cs_creg, 16); 756 zs_loadchannelregs(zc, cs->cs_creg); 757 splx(sps); 758 cs->cs_heldchange = 0; 759 if(cs->cs_heldtbc 760 && (tp->t_state & TS_TTSTOP) == 0) { 761 cs->cs_tbc = cs->cs_heldtbc - 1; 762 zc->zc_data = *cs->cs_tba++; 763 goto again; 764 } 765 } 766 tp->t_state &= ~TS_BUSY; 767 if(tp->t_state & TS_FLUSH) 768 tp->t_state &= ~TS_FLUSH; 769 else ndflush(&tp->t_outq,cs->cs_tba 770 - (caddr_t)tp->t_outq.c_cf); 771 line->l_start(tp); 772 break; 773 774 case ZRING_SINT: 775 /* 776 * Status line change. HFC bit is run in 777 * hardware interrupt, to avoid locking 778 * at splzs here. 779 */ 780 c = ZRING_VALUE(c); 781 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 782 cc = (c & ZSRR0_DCD) != 0; 783 if(line->l_modem(tp, cc) == 0) 784 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 785 cc ? DMBIS : DMBIC); 786 } 787 cs->cs_rr0 = c; 788 break; 789 790 default: 791 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 792 unit >> 1, (unit & 1) + 'a', c); 793 break; 794 } 795 } 796 cs->cs_rbget = get; 797 goto again; 798 } 799 splx(s); 800 return (retval); 801 } 802 803 int 804 zsioctl(dev, cmd, data, flag, p) 805 dev_t dev; 806 u_long cmd; 807 caddr_t data; 808 int flag; 809 struct proc *p; 810 { 811 int unit = ZS_UNIT(dev); 812 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 813 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 814 register int error, s; 815 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 816 817 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 818 if(error >= 0) 819 return(error); 820 error = ttioctl(tp, cmd, data, flag, p); 821 if(error >= 0) 822 return (error); 823 824 switch (cmd) { 825 case TIOCSBRK: 826 s = splzs(); 827 cs->cs_preg[5] |= ZSWR5_BREAK; 828 cs->cs_creg[5] |= ZSWR5_BREAK; 829 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 830 splx(s); 831 break; 832 case TIOCCBRK: 833 s = splzs(); 834 cs->cs_preg[5] &= ~ZSWR5_BREAK; 835 cs->cs_creg[5] &= ~ZSWR5_BREAK; 836 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 837 splx(s); 838 break; 839 case TIOCGFLAGS: { 840 int bits = 0; 841 842 if(cs->cs_softcar) 843 bits |= TIOCFLAG_SOFTCAR; 844 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 845 bits |= TIOCFLAG_CLOCAL; 846 if(cs->cs_creg[3] & ZSWR3_HFC) 847 bits |= TIOCFLAG_CRTSCTS; 848 *(int *)data = bits; 849 break; 850 } 851 case TIOCSFLAGS: { 852 int userbits = 0; 853 854 error = suser(p->p_ucred, &p->p_acflag); 855 if(error != 0) 856 return (EPERM); 857 858 userbits = *(int *)data; 859 860 /* 861 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 862 # defaulting to software flow control. 863 */ 864 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 865 return(EINVAL); 866 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 867 return(ENODEV); 868 869 s = splzs(); 870 if((userbits & TIOCFLAG_SOFTCAR)) { 871 cs->cs_softcar = 1; /* turn on softcar */ 872 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 873 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 874 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 875 } 876 else if(userbits & TIOCFLAG_CLOCAL) { 877 cs->cs_softcar = 0; /* turn off softcar */ 878 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 879 cs->cs_creg[15] |= ZSWR15_DCD_IE; 880 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 881 tp->t_termios.c_cflag |= CLOCAL; 882 } 883 if(userbits & TIOCFLAG_CRTSCTS) { 884 cs->cs_preg[15] |= ZSWR15_CTS_IE; 885 cs->cs_creg[15] |= ZSWR15_CTS_IE; 886 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 887 cs->cs_preg[3] |= ZSWR3_HFC; 888 cs->cs_creg[3] |= ZSWR3_HFC; 889 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 890 tp->t_termios.c_cflag |= CRTSCTS; 891 } 892 else { 893 /* no mdmbuf, so we must want software flow control */ 894 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 895 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 896 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 897 cs->cs_preg[3] &= ~ZSWR3_HFC; 898 cs->cs_creg[3] &= ~ZSWR3_HFC; 899 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 900 tp->t_termios.c_cflag &= ~CRTSCTS; 901 } 902 splx(s); 903 break; 904 } 905 case TIOCSDTR: 906 zs_modem(cs, ZSWR5_DTR, DMBIS); 907 break; 908 case TIOCCDTR: 909 zs_modem(cs, ZSWR5_DTR, DMBIC); 910 break; 911 case TIOCMGET: 912 zs_modem(cs, 0, DMGET); 913 break; 914 case TIOCMSET: 915 case TIOCMBIS: 916 case TIOCMBIC: 917 default: 918 return (ENOTTY); 919 } 920 return (0); 921 } 922 923 /* 924 * Start or restart transmission. 925 */ 926 static void 927 zsstart(tp) 928 register struct tty *tp; 929 { 930 register struct zs_chanstate *cs; 931 register int s, nch; 932 int unit = ZS_UNIT(tp->t_dev); 933 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 934 935 cs = &zi->zi_cs[unit & 1]; 936 s = spltty(); 937 938 /* 939 * If currently active or delaying, no need to do anything. 940 */ 941 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 942 goto out; 943 944 /* 945 * If there are sleepers, and output has drained below low 946 * water mark, awaken. 947 */ 948 if(tp->t_outq.c_cc <= tp->t_lowat) { 949 if(tp->t_state & TS_ASLEEP) { 950 tp->t_state &= ~TS_ASLEEP; 951 wakeup((caddr_t)&tp->t_outq); 952 } 953 selwakeup(&tp->t_wsel); 954 } 955 956 nch = ndqb(&tp->t_outq, 0); /* XXX */ 957 if(nch) { 958 register char *p = tp->t_outq.c_cf; 959 960 /* mark busy, enable tx done interrupts, & send first byte */ 961 tp->t_state |= TS_BUSY; 962 (void) splzs(); 963 cs->cs_preg[1] |= ZSWR1_TIE; 964 cs->cs_creg[1] |= ZSWR1_TIE; 965 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 966 cs->cs_zc->zc_data = *p; 967 cs->cs_tba = p + 1; 968 cs->cs_tbc = nch - 1; 969 } else { 970 /* 971 * Nothing to send, turn off transmit done interrupts. 972 * This is useful if something is doing polled output. 973 */ 974 (void) splzs(); 975 cs->cs_preg[1] &= ~ZSWR1_TIE; 976 cs->cs_creg[1] &= ~ZSWR1_TIE; 977 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 978 } 979 out: 980 splx(s); 981 } 982 983 /* 984 * Stop output, e.g., for ^S or output flush. 985 */ 986 void 987 zsstop(tp, flag) 988 register struct tty *tp; 989 int flag; 990 { 991 register struct zs_chanstate *cs; 992 register int s, unit = ZS_UNIT(tp->t_dev); 993 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 994 995 cs = &zi->zi_cs[unit & 1]; 996 s = splzs(); 997 if(tp->t_state & TS_BUSY) { 998 /* 999 * Device is transmitting; must stop it. 1000 */ 1001 cs->cs_tbc = 0; 1002 if ((tp->t_state & TS_TTSTOP) == 0) 1003 tp->t_state |= TS_FLUSH; 1004 } 1005 splx(s); 1006 } 1007 1008 /* 1009 * Set ZS tty parameters from termios. 1010 * 1011 * This routine makes use of the fact that only registers 1012 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1013 */ 1014 static int 1015 zsparam(tp, t) 1016 register struct tty *tp; 1017 register struct termios *t; 1018 { 1019 int unit = ZS_UNIT(tp->t_dev); 1020 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1021 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1022 int cdiv, clkm, brgm, tcon; 1023 register int tmp, tmp5, cflag, s; 1024 1025 tmp = t->c_ospeed; 1026 tmp5 = t->c_ispeed; 1027 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1028 return(EINVAL); 1029 if(tmp == 0) { 1030 /* stty 0 => drop DTR and RTS */ 1031 zs_modem(cs, 0, DMSET); 1032 return(0); 1033 } 1034 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1035 if (tmp < 0) 1036 return(EINVAL); 1037 tp->t_ispeed = tp->t_ospeed = tmp; 1038 1039 cflag = tp->t_cflag = t->c_cflag; 1040 if (cflag & CSTOPB) 1041 cdiv |= ZSWR4_TWOSB; 1042 else 1043 cdiv |= ZSWR4_ONESB; 1044 if (!(cflag & PARODD)) 1045 cdiv |= ZSWR4_EVENP; 1046 if (cflag & PARENB) 1047 cdiv |= ZSWR4_PARENB; 1048 1049 switch(cflag & CSIZE) { 1050 case CS5: 1051 tmp = ZSWR3_RX_5; 1052 tmp5 = ZSWR5_TX_5; 1053 break; 1054 case CS6: 1055 tmp = ZSWR3_RX_6; 1056 tmp5 = ZSWR5_TX_6; 1057 break; 1058 case CS7: 1059 tmp = ZSWR3_RX_7; 1060 tmp5 = ZSWR5_TX_7; 1061 break; 1062 case CS8: 1063 default: 1064 tmp = ZSWR3_RX_8; 1065 tmp5 = ZSWR5_TX_8; 1066 break; 1067 } 1068 tmp |= ZSWR3_RX_ENABLE; 1069 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1070 1071 /* 1072 * Block interrupts so that state will not 1073 * be altered until we are done setting it up. 1074 */ 1075 s = splzs(); 1076 cs->cs_preg[4] = cdiv; 1077 cs->cs_preg[11] = clkm; 1078 cs->cs_preg[12] = tcon; 1079 cs->cs_preg[13] = tcon >> 8; 1080 cs->cs_preg[14] = brgm; 1081 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1082 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1083 cs->cs_preg[10] = ZSWR10_NRZ; 1084 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1085 1086 /* 1087 * Output hardware flow control on the chip is horrendous: if 1088 * carrier detect drops, the receiver is disabled. Hence we 1089 * can only do this when the carrier is on. 1090 */ 1091 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1092 tmp |= ZSWR3_HFC; 1093 cs->cs_preg[3] = tmp; 1094 cs->cs_preg[5] = tmp5; 1095 1096 /* 1097 * If nothing is being transmitted, set up new current values, 1098 * else mark them as pending. 1099 */ 1100 if(cs->cs_heldchange == 0) { 1101 if (cs->cs_ttyp->t_state & TS_BUSY) { 1102 cs->cs_heldtbc = cs->cs_tbc; 1103 cs->cs_tbc = 0; 1104 cs->cs_heldchange = 1; 1105 } else { 1106 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1107 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1108 } 1109 } 1110 splx(s); 1111 return (0); 1112 } 1113 1114 /* 1115 * search for the best matching baudrate 1116 */ 1117 static int 1118 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1119 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1120 { 1121 int bestdiff, bestbps, source; 1122 1123 bestdiff = bestbps = 0; 1124 unit = (unit & 1) << 2; 1125 for (source = 0; source < 4; ++source) { 1126 long freq = zs_frequencies[unit + source]; 1127 int diff, bps, div, clkm, brgm, tcon; 1128 1129 bps = div = clkm = brgm = tcon = 0; 1130 switch (source) { 1131 case 0: /* BRgen, PCLK */ 1132 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1133 break; 1134 case 1: /* BRgen, RTxC */ 1135 brgm = ZSWR14_BAUD_ENA; 1136 break; 1137 case 2: /* RTxC */ 1138 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1139 break; 1140 case 3: /* TRxC */ 1141 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1142 break; 1143 } 1144 switch (source) { 1145 case 0: 1146 case 1: 1147 div = ZSWR4_CLK_X16; 1148 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1149 tcon = BPS_TO_TCONST(freq, wanted); 1150 if (tcon < 0) 1151 tcon = 0; 1152 bps = TCONST_TO_BPS(freq, tcon); 1153 break; 1154 case 2: 1155 case 3: 1156 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1157 int b2 = freq / 32, d2 = abs(b2 - wanted); 1158 int b3 = freq / 64, d3 = abs(b3 - wanted); 1159 1160 if (d1 < d2 && d1 < d3) { 1161 div = ZSWR4_CLK_X16; 1162 bps = b1; 1163 } else if (d2 < d3 && d2 < d1) { 1164 div = ZSWR4_CLK_X32; 1165 bps = b2; 1166 } else { 1167 div = ZSWR4_CLK_X64; 1168 bps = b3; 1169 } 1170 brgm = tcon = 0; 1171 break; 1172 } 1173 } 1174 diff = abs(bps - wanted); 1175 if (!source || diff < bestdiff) { 1176 *divisor = div; 1177 *clockmode = clkm; 1178 *brgenmode = brgm; 1179 *timeconst = tcon; 1180 bestbps = bps; 1181 bestdiff = diff; 1182 if (diff == 0) 1183 break; 1184 } 1185 } 1186 /* Allow deviations upto 5% */ 1187 if (20 * bestdiff > wanted) 1188 return -1; 1189 return bestbps; 1190 } 1191 1192 /* 1193 * Raise or lower modem control (DTR/RTS) signals. If a character is 1194 * in transmission, the change is deferred. 1195 */ 1196 static int 1197 zs_modem(cs, bits, how) 1198 struct zs_chanstate *cs; 1199 int bits, how; 1200 { 1201 int s, mbits; 1202 1203 bits &= ZSWR5_DTR | ZSWR5_RTS; 1204 1205 s = splzs(); 1206 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1207 1208 switch(how) { 1209 case DMSET: 1210 mbits = bits; 1211 break; 1212 case DMBIS: 1213 mbits |= bits; 1214 break; 1215 case DMBIC: 1216 mbits &= ~bits; 1217 break; 1218 case DMGET: 1219 splx(s); 1220 return(mbits); 1221 } 1222 1223 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1224 if(cs->cs_heldchange == 0) { 1225 if(cs->cs_ttyp->t_state & TS_BUSY) { 1226 cs->cs_heldtbc = cs->cs_tbc; 1227 cs->cs_tbc = 0; 1228 cs->cs_heldchange = 1; 1229 } 1230 else { 1231 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1232 } 1233 } 1234 splx(s); 1235 return(0); 1236 } 1237 1238 /* 1239 * Write the given register set to the given zs channel in the proper order. 1240 * The channel must not be transmitting at the time. The receiver will 1241 * be disabled for the time it takes to write all the registers. 1242 */ 1243 static void 1244 zs_loadchannelregs(zc, reg) 1245 volatile struct zschan *zc; 1246 u_char *reg; 1247 { 1248 int i; 1249 1250 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1251 i = zc->zc_data; /* drain fifo */ 1252 i = zc->zc_data; 1253 i = zc->zc_data; 1254 ZS_WRITE(zc, 4, reg[4]); 1255 ZS_WRITE(zc, 10, reg[10]); 1256 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1257 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1258 ZS_WRITE(zc, 1, reg[1]); 1259 ZS_WRITE(zc, 9, reg[9]); 1260 ZS_WRITE(zc, 11, reg[11]); 1261 ZS_WRITE(zc, 12, reg[12]); 1262 ZS_WRITE(zc, 13, reg[13]); 1263 ZS_WRITE(zc, 14, reg[14]); 1264 ZS_WRITE(zc, 15, reg[15]); 1265 ZS_WRITE(zc, 3, reg[3]); 1266 ZS_WRITE(zc, 5, reg[5]); 1267 } 1268 #endif /* NZS > 1 */ 1269