1 /* $NetBSD: zs.c,v 1.31 2000/03/29 14:19:23 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 L. Weppelman (Atari modifications) 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * 4. Neither the name of the University nor the names of its contributors 31 * may be used to endorse or promote products derived from this software 32 * without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 40 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 42 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 43 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 44 * SUCH DAMAGE. 45 * 46 * @(#)zs.c 8.1 (Berkeley) 7/19/93 47 */ 48 49 /* 50 * Zilog Z8530 (ZSCC) driver. 51 * 52 * Runs two tty ports (modem2 and serial2) on zs0. 53 * 54 * This driver knows far too much about chip to usage mappings. 55 */ 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/proc.h> 59 #include <sys/device.h> 60 #include <sys/conf.h> 61 #include <sys/file.h> 62 #include <sys/ioctl.h> 63 #include <sys/malloc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/kernel.h> 67 #include <sys/syslog.h> 68 69 #include <machine/cpu.h> 70 #include <machine/iomap.h> 71 #include <machine/scu.h> 72 #include <machine/mfp.h> 73 #include <atari/dev/ym2149reg.h> 74 75 #include <dev/ic/z8530reg.h> 76 #include <atari/dev/zsvar.h> 77 #include "zs.h" 78 #if NZS > 1 79 #error "This driver supports only 1 85C30!" 80 #endif 81 82 #if NZS > 0 83 84 #define PCLK (8053976) /* PCLK pin input clock rate */ 85 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 86 87 #define splzs spl5 88 89 /* 90 * Software state per found chip. 91 */ 92 struct zs_softc { 93 struct device zi_dev; /* base device */ 94 volatile struct zsdevice *zi_zs; /* chip registers */ 95 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 96 }; 97 98 static u_char cb_scheduled = 0; /* Already asked for callback? */ 99 /* 100 * Define the registers for a closed port 101 */ 102 static u_char zs_init_regs[16] = { 103 /* 0 */ 0, 104 /* 1 */ 0, 105 /* 2 */ 0x60, 106 /* 3 */ 0, 107 /* 4 */ 0, 108 /* 5 */ 0, 109 /* 6 */ 0, 110 /* 7 */ 0, 111 /* 8 */ 0, 112 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 113 /* 10 */ ZSWR10_NRZ, 114 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115 /* 12 */ 0, 116 /* 13 */ 0, 117 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 118 /* 15 */ 0 119 }; 120 121 /* 122 * Define the machine dependant clock frequencies 123 * If BRgen feeds sender/receiver we always use a 124 * divisor 16, therefor the division by 16 can as 125 * well be done here. 126 */ 127 static u_long zs_freqs_tt[] = { 128 /* 129 * Atari TT, RTxCB is generated by TT-MFP timer C, 130 * which is set to 307.2KHz during initialisation 131 * and never changed afterwards. 132 */ 133 PCLK/16, /* BRgen, PCLK, divisor 16 */ 134 229500, /* BRgen, RTxCA, divisor 16 */ 135 3672000, /* RTxCA, from PCLK4 */ 136 0, /* TRxCA, external */ 137 138 PCLK/16, /* BRgen, PCLK, divisor 16 */ 139 19200, /* BRgen, RTxCB, divisor 16 */ 140 307200, /* RTxCB, from TT-MFP TCO */ 141 2457600 /* TRxCB, from BCLK */ 142 }; 143 144 static u_long zs_freqs_falcon[] = { 145 /* 146 * Atari Falcon, XXX no specs available, this might be wrong 147 */ 148 PCLK/16, /* BRgen, PCLK, divisor 16 */ 149 229500, /* BRgen, RTxCA, divisor 16 */ 150 3672000, /* RTxCA, ??? */ 151 0, /* TRxCA, external */ 152 153 PCLK/16, /* BRgen, PCLK, divisor 16 */ 154 229500, /* BRgen, RTxCB, divisor 16 */ 155 3672000, /* RTxCB, ??? */ 156 2457600 /* TRxCB, ??? */ 157 }; 158 159 static u_long zs_freqs_hades[] = { 160 /* 161 * XXX: Channel-A unchecked!!!!! 162 */ 163 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 164 229500, /* BRgen, RTxCA, divisor 16 */ 165 3672000, /* RTxCA, from PCLK4 */ 166 0, /* TRxCA, external */ 167 168 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 169 235550, /* BRgen, RTxCB, divisor 16 */ 170 3768800, /* RTxCB, 3.7688MHz */ 171 3768800 /* TRxCB, 3.7688MHz */ 172 }; 173 174 static u_long zs_freqs_generic[] = { 175 /* 176 * other machines, assume only PCLK is available 177 */ 178 PCLK/16, /* BRgen, PCLK, divisor 16 */ 179 0, /* BRgen, RTxCA, divisor 16 */ 180 0, /* RTxCA, unknown */ 181 0, /* TRxCA, unknown */ 182 183 PCLK/16, /* BRgen, PCLK, divisor 16 */ 184 0, /* BRgen, RTxCB, divisor 16 */ 185 0, /* RTxCB, unknown */ 186 0 /* TRxCB, unknown */ 187 }; 188 static u_long *zs_frequencies; 189 190 /* Definition of the driver for autoconfig. */ 191 static int zsmatch __P((struct device *, struct cfdata *, void *)); 192 static void zsattach __P((struct device *, struct device *, void *)); 193 194 struct cfattach zs_ca = { 195 sizeof(struct zs_softc), zsmatch, zsattach 196 }; 197 198 extern struct cfdriver zs_cd; 199 200 /* {b,c}devsw[] function prototypes */ 201 dev_type_open(zsopen); 202 dev_type_close(zsclose); 203 dev_type_read(zsread); 204 dev_type_write(zswrite); 205 dev_type_ioctl(zsioctl); 206 dev_type_tty(zstty); 207 208 /* Interrupt handlers. */ 209 int zshard __P((long)); 210 static int zssoft __P((long)); 211 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 212 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 213 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 214 215 static struct zs_chanstate *zslist; 216 217 /* Routines called from other code. */ 218 static void zsstart __P((struct tty *)); 219 void zsstop __P((struct tty *, int)); 220 221 /* Routines purely local to this driver. */ 222 static void zsoverrun __P((int, long *, char *)); 223 static int zsparam __P((struct tty *, struct termios *)); 224 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 225 static int zs_modem __P((struct zs_chanstate *, int, int)); 226 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 227 static void zs_shutdown __P((struct zs_chanstate *)); 228 229 static int zsshortcuts; /* number of "shortcut" software interrupts */ 230 231 static int 232 zsmatch(pdp, cfp, auxp) 233 struct device *pdp; 234 struct cfdata *cfp; 235 void *auxp; 236 { 237 static int zs_matched = 0; 238 239 if(strcmp("zs", auxp) || zs_matched) 240 return(0); 241 zs_matched = 1; 242 return(1); 243 } 244 245 /* 246 * Attach a found zs. 247 */ 248 static void 249 zsattach(parent, dev, aux) 250 struct device *parent; 251 struct device *dev; 252 void *aux; 253 { 254 register struct zs_softc *zi; 255 register struct zs_chanstate *cs; 256 register volatile struct zsdevice *addr; 257 char tmp; 258 259 addr = (struct zsdevice *)AD_SCC; 260 zi = (struct zs_softc *)dev; 261 zi->zi_zs = addr; 262 cs = zi->zi_cs; 263 264 /* 265 * Get the command register into a known state. 266 */ 267 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 268 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 269 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 270 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 271 272 /* 273 * Do a hardware reset. 274 */ 275 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 276 delay(50000); /*enough ? */ 277 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 278 279 /* 280 * Initialize both channels 281 */ 282 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 283 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 284 285 if(machineid & ATARI_TT) { 286 /* 287 * ininitialise TT-MFP timer C: 307200Hz 288 * timer C and D share one control register: 289 * bits 0-2 control timer D 290 * bits 4-6 control timer C 291 */ 292 int cr = MFP2->mf_tcdcr & 7; 293 MFP2->mf_tcdcr = cr; /* stop timer C */ 294 MFP2->mf_tcdr = 1; /* counter 1 */ 295 cr |= T_Q004 << 4; /* divisor 4 */ 296 MFP2->mf_tcdcr = cr; /* start timer C */ 297 /* 298 * enable scc related interrupts 299 */ 300 SCU->vme_mask |= SCU_SCC; 301 302 zs_frequencies = zs_freqs_tt; 303 } else if (machineid & ATARI_FALCON) { 304 zs_frequencies = zs_freqs_falcon; 305 } else if (machineid & ATARI_HADES) { 306 zs_frequencies = zs_freqs_hades; 307 } else { 308 zs_frequencies = zs_freqs_generic; 309 } 310 311 /* link into interrupt list with order (A,B) (B=A+1) */ 312 cs[0].cs_next = &cs[1]; 313 cs[1].cs_next = zslist; 314 zslist = cs; 315 316 cs->cs_unit = 0; 317 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 318 cs++; 319 cs->cs_unit = 1; 320 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 321 322 printf(": serial2 on channel a and modem2 on channel b\n"); 323 } 324 325 /* 326 * Open a zs serial port. 327 */ 328 int 329 zsopen(dev, flags, mode, p) 330 dev_t dev; 331 int flags; 332 int mode; 333 struct proc *p; 334 { 335 register struct tty *tp; 336 register struct zs_chanstate *cs; 337 struct zs_softc *zi; 338 int unit = ZS_UNIT(dev); 339 int zs = unit >> 1; 340 int error, s; 341 342 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 343 return (ENXIO); 344 cs = &zi->zi_cs[unit & 1]; 345 346 /* 347 * When port A (ser02) is selected on the TT, make sure 348 * the port is enabled. 349 */ 350 if((machineid & ATARI_TT) && !(unit & 1)) 351 ym2149_ser2(1); 352 353 if (cs->cs_rbuf == NULL) { 354 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 355 M_WAITOK); 356 } 357 358 tp = cs->cs_ttyp; 359 if(tp == NULL) { 360 cs->cs_ttyp = tp = ttymalloc(); 361 tty_attach(tp); 362 tp->t_dev = dev; 363 tp->t_oproc = zsstart; 364 tp->t_param = zsparam; 365 } 366 367 if ((tp->t_state & TS_ISOPEN) && 368 (tp->t_state & TS_XCLUDE) && 369 p->p_ucred->cr_uid != 0) 370 return (EBUSY); 371 372 s = spltty(); 373 374 /* 375 * Do the following iff this is a first open. 376 */ 377 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 378 if(tp->t_ispeed == 0) { 379 tp->t_iflag = TTYDEF_IFLAG; 380 tp->t_oflag = TTYDEF_OFLAG; 381 tp->t_cflag = TTYDEF_CFLAG; 382 tp->t_lflag = TTYDEF_LFLAG; 383 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 384 } 385 ttychars(tp); 386 ttsetwater(tp); 387 388 (void)zsparam(tp, &tp->t_termios); 389 390 /* 391 * Turn on DTR. We must always do this, even if carrier is not 392 * present, because otherwise we'd have to use TIOCSDTR 393 * immediately after setting CLOCAL, which applications do not 394 * expect. We always assert DTR while the device is open 395 * unless explicitly requested to deassert it. 396 */ 397 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 398 /* May never get a status intr. if DCD already on. -gwr */ 399 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 400 tp->t_state |= TS_CARR_ON; 401 if(cs->cs_softcar) 402 tp->t_state |= TS_CARR_ON; 403 } 404 405 splx(s); 406 407 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 408 if (error) 409 goto bad; 410 411 error = linesw[tp->t_line].l_open(dev, tp); 412 if(error) 413 goto bad; 414 return (0); 415 416 bad: 417 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 418 /* 419 * We failed to open the device, and nobody else had it opened. 420 * Clean up the state as appropriate. 421 */ 422 zs_shutdown(cs); 423 } 424 return(error); 425 } 426 427 /* 428 * Close a zs serial port. 429 */ 430 int 431 zsclose(dev, flags, mode, p) 432 dev_t dev; 433 int flags; 434 int mode; 435 struct proc *p; 436 { 437 register struct zs_chanstate *cs; 438 register struct tty *tp; 439 struct zs_softc *zi; 440 int unit = ZS_UNIT(dev); 441 442 zi = zs_cd.cd_devs[unit >> 1]; 443 cs = &zi->zi_cs[unit & 1]; 444 tp = cs->cs_ttyp; 445 446 linesw[tp->t_line].l_close(tp, flags); 447 ttyclose(tp); 448 449 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 450 /* 451 * Although we got a last close, the device may still be in 452 * use; e.g. if this was the dialout node, and there are still 453 * processes waiting for carrier on the non-dialout node. 454 */ 455 zs_shutdown(cs); 456 } 457 return (0); 458 } 459 460 /* 461 * Read/write zs serial port. 462 */ 463 int 464 zsread(dev, uio, flags) 465 dev_t dev; 466 struct uio *uio; 467 int flags; 468 { 469 register struct zs_chanstate *cs; 470 register struct zs_softc *zi; 471 register struct tty *tp; 472 int unit; 473 474 unit = ZS_UNIT(dev); 475 zi = zs_cd.cd_devs[unit >> 1]; 476 cs = &zi->zi_cs[unit & 1]; 477 tp = cs->cs_ttyp; 478 479 return(linesw[tp->t_line].l_read(tp, uio, flags)); 480 } 481 482 int 483 zswrite(dev, uio, flags) 484 dev_t dev; 485 struct uio *uio; 486 int flags; 487 { 488 register struct zs_chanstate *cs; 489 register struct zs_softc *zi; 490 register struct tty *tp; 491 int unit; 492 493 unit = ZS_UNIT(dev); 494 zi = zs_cd.cd_devs[unit >> 1]; 495 cs = &zi->zi_cs[unit & 1]; 496 tp = cs->cs_ttyp; 497 498 return(linesw[tp->t_line].l_write(tp, uio, flags)); 499 } 500 501 struct tty * 502 zstty(dev) 503 dev_t dev; 504 { 505 register struct zs_chanstate *cs; 506 register struct zs_softc *zi; 507 int unit; 508 509 unit = ZS_UNIT(dev); 510 zi = zs_cd.cd_devs[unit >> 1]; 511 cs = &zi->zi_cs[unit & 1]; 512 return(cs->cs_ttyp); 513 } 514 515 /* 516 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 517 * channels are kept in (A,B) pairs. 518 * 519 * Do just a little, then get out; set a software interrupt if more 520 * work is needed. 521 * 522 * We deliberately ignore the vectoring Zilog gives us, and match up 523 * only the number of `reset interrupt under service' operations, not 524 * the order. 525 */ 526 527 int 528 zshard(sr) 529 long sr; 530 { 531 register struct zs_chanstate *a; 532 #define b (a + 1) 533 register volatile struct zschan *zc; 534 register int rr3, intflags = 0, v, i; 535 536 do { 537 intflags &= ~4; 538 for(a = zslist; a != NULL; a = b->cs_next) { 539 rr3 = ZS_READ(a->cs_zc, 3); 540 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 541 intflags |= 4|2; 542 zc = a->cs_zc; 543 i = a->cs_rbput; 544 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 545 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 546 intflags |= 1; 547 } 548 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 549 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 550 intflags |= 1; 551 } 552 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 553 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 554 intflags |= 1; 555 } 556 a->cs_rbput = i; 557 } 558 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 559 intflags |= 4|2; 560 zc = b->cs_zc; 561 i = b->cs_rbput; 562 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 563 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 564 intflags |= 1; 565 } 566 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 567 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 568 intflags |= 1; 569 } 570 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 571 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 572 intflags |= 1; 573 } 574 b->cs_rbput = i; 575 } 576 } 577 } while(intflags & 4); 578 #undef b 579 580 if(intflags & 1) { 581 if(BASEPRI(sr)) { 582 spl1(); 583 zsshortcuts++; 584 return(zssoft(sr)); 585 } 586 else if(!cb_scheduled) { 587 cb_scheduled++; 588 add_sicallback((si_farg)zssoft, 0, 0); 589 } 590 } 591 return(intflags & 2); 592 } 593 594 static int 595 zsrint(cs, zc) 596 register struct zs_chanstate *cs; 597 register volatile struct zschan *zc; 598 { 599 register int c; 600 601 /* 602 * First read the status, because read of the received char 603 * destroy the status of this char. 604 */ 605 c = ZS_READ(zc, 1); 606 c |= (zc->zc_data << 8); 607 608 /* clear receive error & interrupt condition */ 609 zc->zc_csr = ZSWR0_RESET_ERRORS; 610 zc->zc_csr = ZSWR0_CLR_INTR; 611 612 return(ZRING_MAKE(ZRING_RINT, c)); 613 } 614 615 static int 616 zsxint(cs, zc) 617 register struct zs_chanstate *cs; 618 register volatile struct zschan *zc; 619 { 620 register int i = cs->cs_tbc; 621 622 if(i == 0) { 623 zc->zc_csr = ZSWR0_RESET_TXINT; 624 zc->zc_csr = ZSWR0_CLR_INTR; 625 return(ZRING_MAKE(ZRING_XINT, 0)); 626 } 627 cs->cs_tbc = i - 1; 628 zc->zc_data = *cs->cs_tba++; 629 zc->zc_csr = ZSWR0_CLR_INTR; 630 return (0); 631 } 632 633 static int 634 zssint(cs, zc) 635 register struct zs_chanstate *cs; 636 register volatile struct zschan *zc; 637 { 638 register int rr0; 639 640 rr0 = zc->zc_csr; 641 zc->zc_csr = ZSWR0_RESET_STATUS; 642 zc->zc_csr = ZSWR0_CLR_INTR; 643 /* 644 * The chip's hardware flow control is, as noted in zsreg.h, 645 * busted---if the DCD line goes low the chip shuts off the 646 * receiver (!). If we want hardware CTS flow control but do 647 * not have it, and carrier is now on, turn HFC on; if we have 648 * HFC now but carrier has gone low, turn it off. 649 */ 650 if(rr0 & ZSRR0_DCD) { 651 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 652 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 653 cs->cs_creg[3] |= ZSWR3_HFC; 654 ZS_WRITE(zc, 3, cs->cs_creg[3]); 655 } 656 } 657 else { 658 if (cs->cs_creg[3] & ZSWR3_HFC) { 659 cs->cs_creg[3] &= ~ZSWR3_HFC; 660 ZS_WRITE(zc, 3, cs->cs_creg[3]); 661 } 662 } 663 return(ZRING_MAKE(ZRING_SINT, rr0)); 664 } 665 666 /* 667 * Print out a ring or fifo overrun error message. 668 */ 669 static void 670 zsoverrun(unit, ptime, what) 671 int unit; 672 long *ptime; 673 char *what; 674 { 675 676 if(*ptime != time.tv_sec) { 677 *ptime = time.tv_sec; 678 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 679 (unit & 1) + 'a', what); 680 } 681 } 682 683 /* 684 * ZS software interrupt. Scan all channels for deferred interrupts. 685 */ 686 int 687 zssoft(sr) 688 long sr; 689 { 690 register struct zs_chanstate *cs; 691 register volatile struct zschan *zc; 692 register struct linesw *line; 693 register struct tty *tp; 694 register int get, n, c, cc, unit, s; 695 int retval = 0; 696 697 cb_scheduled = 0; 698 s = spltty(); 699 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 700 get = cs->cs_rbget; 701 again: 702 n = cs->cs_rbput; /* atomic */ 703 if(get == n) /* nothing more on this line */ 704 continue; 705 retval = 1; 706 unit = cs->cs_unit; /* set up to handle interrupts */ 707 zc = cs->cs_zc; 708 tp = cs->cs_ttyp; 709 line = &linesw[tp->t_line]; 710 /* 711 * Compute the number of interrupts in the receive ring. 712 * If the count is overlarge, we lost some events, and 713 * must advance to the first valid one. It may get 714 * overwritten if more data are arriving, but this is 715 * too expensive to check and gains nothing (we already 716 * lost out; all we can do at this point is trade one 717 * kind of loss for another). 718 */ 719 n -= get; 720 if(n > ZLRB_RING_SIZE) { 721 zsoverrun(unit, &cs->cs_rotime, "ring"); 722 get += n - ZLRB_RING_SIZE; 723 n = ZLRB_RING_SIZE; 724 } 725 while(--n >= 0) { 726 /* race to keep ahead of incoming interrupts */ 727 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 728 switch (ZRING_TYPE(c)) { 729 730 case ZRING_RINT: 731 c = ZRING_VALUE(c); 732 if(c & ZSRR1_DO) 733 zsoverrun(unit, &cs->cs_fotime, "fifo"); 734 cc = c >> 8; 735 if(c & ZSRR1_FE) 736 cc |= TTY_FE; 737 if(c & ZSRR1_PE) 738 cc |= TTY_PE; 739 line->l_rint(cc, tp); 740 break; 741 742 case ZRING_XINT: 743 /* 744 * Transmit done: change registers and resume, 745 * or clear BUSY. 746 */ 747 if(cs->cs_heldchange) { 748 int sps; 749 750 sps = splzs(); 751 c = zc->zc_csr; 752 if((c & ZSRR0_DCD) == 0) 753 cs->cs_preg[3] &= ~ZSWR3_HFC; 754 bcopy((caddr_t)cs->cs_preg, 755 (caddr_t)cs->cs_creg, 16); 756 zs_loadchannelregs(zc, cs->cs_creg); 757 splx(sps); 758 cs->cs_heldchange = 0; 759 if(cs->cs_heldtbc 760 && (tp->t_state & TS_TTSTOP) == 0) { 761 cs->cs_tbc = cs->cs_heldtbc - 1; 762 zc->zc_data = *cs->cs_tba++; 763 goto again; 764 } 765 } 766 tp->t_state &= ~TS_BUSY; 767 if(tp->t_state & TS_FLUSH) 768 tp->t_state &= ~TS_FLUSH; 769 else ndflush(&tp->t_outq,cs->cs_tba 770 - (caddr_t)tp->t_outq.c_cf); 771 line->l_start(tp); 772 break; 773 774 case ZRING_SINT: 775 /* 776 * Status line change. HFC bit is run in 777 * hardware interrupt, to avoid locking 778 * at splzs here. 779 */ 780 c = ZRING_VALUE(c); 781 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 782 cc = (c & ZSRR0_DCD) != 0; 783 if(line->l_modem(tp, cc) == 0) 784 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 785 cc ? DMBIS : DMBIC); 786 } 787 cs->cs_rr0 = c; 788 break; 789 790 default: 791 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 792 unit >> 1, (unit & 1) + 'a', c); 793 break; 794 } 795 } 796 cs->cs_rbget = get; 797 goto again; 798 } 799 splx(s); 800 return (retval); 801 } 802 803 int 804 zsioctl(dev, cmd, data, flag, p) 805 dev_t dev; 806 u_long cmd; 807 caddr_t data; 808 int flag; 809 struct proc *p; 810 { 811 int unit = ZS_UNIT(dev); 812 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 813 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 814 register int error, s; 815 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 816 817 error = linesw[tp->t_line].l_ioctl(tp, cmd, data, flag, p); 818 if(error >= 0) 819 return(error); 820 error = ttioctl(tp, cmd, data, flag, p); 821 if(error >= 0) 822 return (error); 823 824 switch (cmd) { 825 case TIOCSBRK: 826 s = splzs(); 827 cs->cs_preg[5] |= ZSWR5_BREAK; 828 cs->cs_creg[5] |= ZSWR5_BREAK; 829 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 830 splx(s); 831 break; 832 case TIOCCBRK: 833 s = splzs(); 834 cs->cs_preg[5] &= ~ZSWR5_BREAK; 835 cs->cs_creg[5] &= ~ZSWR5_BREAK; 836 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 837 splx(s); 838 break; 839 case TIOCGFLAGS: { 840 int bits = 0; 841 842 if(cs->cs_softcar) 843 bits |= TIOCFLAG_SOFTCAR; 844 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 845 bits |= TIOCFLAG_CLOCAL; 846 if(cs->cs_creg[3] & ZSWR3_HFC) 847 bits |= TIOCFLAG_CRTSCTS; 848 *(int *)data = bits; 849 break; 850 } 851 case TIOCSFLAGS: { 852 int userbits = 0; 853 854 error = suser(p->p_ucred, &p->p_acflag); 855 if(error != 0) 856 return (EPERM); 857 858 userbits = *(int *)data; 859 860 /* 861 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 862 # defaulting to software flow control. 863 */ 864 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 865 return(EINVAL); 866 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 867 return(ENODEV); 868 869 s = splzs(); 870 if((userbits & TIOCFLAG_SOFTCAR)) { 871 cs->cs_softcar = 1; /* turn on softcar */ 872 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 873 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 874 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 875 } 876 else if(userbits & TIOCFLAG_CLOCAL) { 877 cs->cs_softcar = 0; /* turn off softcar */ 878 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 879 cs->cs_creg[15] |= ZSWR15_DCD_IE; 880 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 881 tp->t_termios.c_cflag |= CLOCAL; 882 } 883 if(userbits & TIOCFLAG_CRTSCTS) { 884 cs->cs_preg[15] |= ZSWR15_CTS_IE; 885 cs->cs_creg[15] |= ZSWR15_CTS_IE; 886 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 887 cs->cs_preg[3] |= ZSWR3_HFC; 888 cs->cs_creg[3] |= ZSWR3_HFC; 889 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 890 tp->t_termios.c_cflag |= CRTSCTS; 891 } 892 else { 893 /* no mdmbuf, so we must want software flow control */ 894 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 895 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 896 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 897 cs->cs_preg[3] &= ~ZSWR3_HFC; 898 cs->cs_creg[3] &= ~ZSWR3_HFC; 899 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 900 tp->t_termios.c_cflag &= ~CRTSCTS; 901 } 902 splx(s); 903 break; 904 } 905 case TIOCSDTR: 906 zs_modem(cs, ZSWR5_DTR, DMBIS); 907 break; 908 case TIOCCDTR: 909 zs_modem(cs, ZSWR5_DTR, DMBIC); 910 break; 911 case TIOCMGET: 912 zs_modem(cs, 0, DMGET); 913 break; 914 case TIOCMSET: 915 case TIOCMBIS: 916 case TIOCMBIC: 917 default: 918 return (ENOTTY); 919 } 920 return (0); 921 } 922 923 /* 924 * Start or restart transmission. 925 */ 926 static void 927 zsstart(tp) 928 register struct tty *tp; 929 { 930 register struct zs_chanstate *cs; 931 register int s, nch; 932 int unit = ZS_UNIT(tp->t_dev); 933 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 934 935 cs = &zi->zi_cs[unit & 1]; 936 s = spltty(); 937 938 /* 939 * If currently active or delaying, no need to do anything. 940 */ 941 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 942 goto out; 943 944 /* 945 * If there are sleepers, and output has drained below low 946 * water mark, awaken. 947 */ 948 if(tp->t_outq.c_cc <= tp->t_lowat) { 949 if(tp->t_state & TS_ASLEEP) { 950 tp->t_state &= ~TS_ASLEEP; 951 wakeup((caddr_t)&tp->t_outq); 952 } 953 selwakeup(&tp->t_wsel); 954 } 955 956 nch = ndqb(&tp->t_outq, 0); /* XXX */ 957 if(nch) { 958 register char *p = tp->t_outq.c_cf; 959 960 /* mark busy, enable tx done interrupts, & send first byte */ 961 tp->t_state |= TS_BUSY; 962 (void) splzs(); 963 cs->cs_preg[1] |= ZSWR1_TIE; 964 cs->cs_creg[1] |= ZSWR1_TIE; 965 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 966 cs->cs_zc->zc_data = *p; 967 cs->cs_tba = p + 1; 968 cs->cs_tbc = nch - 1; 969 } else { 970 /* 971 * Nothing to send, turn off transmit done interrupts. 972 * This is useful if something is doing polled output. 973 */ 974 (void) splzs(); 975 cs->cs_preg[1] &= ~ZSWR1_TIE; 976 cs->cs_creg[1] &= ~ZSWR1_TIE; 977 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 978 } 979 out: 980 splx(s); 981 } 982 983 /* 984 * Stop output, e.g., for ^S or output flush. 985 */ 986 void 987 zsstop(tp, flag) 988 register struct tty *tp; 989 int flag; 990 { 991 register struct zs_chanstate *cs; 992 register int s, unit = ZS_UNIT(tp->t_dev); 993 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 994 995 cs = &zi->zi_cs[unit & 1]; 996 s = splzs(); 997 if(tp->t_state & TS_BUSY) { 998 /* 999 * Device is transmitting; must stop it. 1000 */ 1001 cs->cs_tbc = 0; 1002 if ((tp->t_state & TS_TTSTOP) == 0) 1003 tp->t_state |= TS_FLUSH; 1004 } 1005 splx(s); 1006 } 1007 1008 static void 1009 zs_shutdown(cs) 1010 struct zs_chanstate *cs; 1011 { 1012 struct tty *tp = cs->cs_ttyp; 1013 int s; 1014 1015 s = splzs(); 1016 1017 /* 1018 * Hang up if necessary. Wait a bit, so the other side has time to 1019 * notice even if we immediately open the port again. 1020 */ 1021 if(tp->t_cflag & HUPCL) { 1022 zs_modem(cs, 0, DMSET); 1023 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 1024 } 1025 1026 /* Clear any break condition set with TIOCSBRK. */ 1027 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1028 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1029 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1030 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1031 } 1032 1033 /* 1034 * Drop all lines and cancel interrupts 1035 */ 1036 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1037 splx(s); 1038 } 1039 1040 /* 1041 * Set ZS tty parameters from termios. 1042 * 1043 * This routine makes use of the fact that only registers 1044 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1045 */ 1046 static int 1047 zsparam(tp, t) 1048 register struct tty *tp; 1049 register struct termios *t; 1050 { 1051 int unit = ZS_UNIT(tp->t_dev); 1052 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1053 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1054 int cdiv, clkm, brgm, tcon; 1055 register int tmp, tmp5, cflag, s; 1056 1057 tmp = t->c_ospeed; 1058 tmp5 = t->c_ispeed; 1059 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1060 return(EINVAL); 1061 if(tmp == 0) { 1062 /* stty 0 => drop DTR and RTS */ 1063 zs_modem(cs, 0, DMSET); 1064 return(0); 1065 } 1066 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1067 if (tmp < 0) 1068 return(EINVAL); 1069 tp->t_ispeed = tp->t_ospeed = tmp; 1070 1071 cflag = tp->t_cflag = t->c_cflag; 1072 if (cflag & CSTOPB) 1073 cdiv |= ZSWR4_TWOSB; 1074 else 1075 cdiv |= ZSWR4_ONESB; 1076 if (!(cflag & PARODD)) 1077 cdiv |= ZSWR4_EVENP; 1078 if (cflag & PARENB) 1079 cdiv |= ZSWR4_PARENB; 1080 1081 switch(cflag & CSIZE) { 1082 case CS5: 1083 tmp = ZSWR3_RX_5; 1084 tmp5 = ZSWR5_TX_5; 1085 break; 1086 case CS6: 1087 tmp = ZSWR3_RX_6; 1088 tmp5 = ZSWR5_TX_6; 1089 break; 1090 case CS7: 1091 tmp = ZSWR3_RX_7; 1092 tmp5 = ZSWR5_TX_7; 1093 break; 1094 case CS8: 1095 default: 1096 tmp = ZSWR3_RX_8; 1097 tmp5 = ZSWR5_TX_8; 1098 break; 1099 } 1100 tmp |= ZSWR3_RX_ENABLE; 1101 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1102 1103 /* 1104 * Block interrupts so that state will not 1105 * be altered until we are done setting it up. 1106 */ 1107 s = splzs(); 1108 cs->cs_preg[4] = cdiv; 1109 cs->cs_preg[11] = clkm; 1110 cs->cs_preg[12] = tcon; 1111 cs->cs_preg[13] = tcon >> 8; 1112 cs->cs_preg[14] = brgm; 1113 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1114 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1115 cs->cs_preg[10] = ZSWR10_NRZ; 1116 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1117 1118 /* 1119 * Output hardware flow control on the chip is horrendous: if 1120 * carrier detect drops, the receiver is disabled. Hence we 1121 * can only do this when the carrier is on. 1122 */ 1123 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1124 tmp |= ZSWR3_HFC; 1125 cs->cs_preg[3] = tmp; 1126 cs->cs_preg[5] = tmp5; 1127 1128 /* 1129 * If nothing is being transmitted, set up new current values, 1130 * else mark them as pending. 1131 */ 1132 if(cs->cs_heldchange == 0) { 1133 if (cs->cs_ttyp->t_state & TS_BUSY) { 1134 cs->cs_heldtbc = cs->cs_tbc; 1135 cs->cs_tbc = 0; 1136 cs->cs_heldchange = 1; 1137 } else { 1138 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1139 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1140 } 1141 } 1142 splx(s); 1143 return (0); 1144 } 1145 1146 /* 1147 * search for the best matching baudrate 1148 */ 1149 static int 1150 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1151 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1152 { 1153 int bestdiff, bestbps, source; 1154 1155 bestdiff = bestbps = 0; 1156 unit = (unit & 1) << 2; 1157 for (source = 0; source < 4; ++source) { 1158 long freq = zs_frequencies[unit + source]; 1159 int diff, bps, div, clkm, brgm, tcon; 1160 1161 bps = div = clkm = brgm = tcon = 0; 1162 switch (source) { 1163 case 0: /* BRgen, PCLK */ 1164 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1165 break; 1166 case 1: /* BRgen, RTxC */ 1167 brgm = ZSWR14_BAUD_ENA; 1168 break; 1169 case 2: /* RTxC */ 1170 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1171 break; 1172 case 3: /* TRxC */ 1173 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1174 break; 1175 } 1176 switch (source) { 1177 case 0: 1178 case 1: 1179 div = ZSWR4_CLK_X16; 1180 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1181 tcon = BPS_TO_TCONST(freq, wanted); 1182 if (tcon < 0) 1183 tcon = 0; 1184 bps = TCONST_TO_BPS(freq, tcon); 1185 break; 1186 case 2: 1187 case 3: 1188 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1189 int b2 = freq / 32, d2 = abs(b2 - wanted); 1190 int b3 = freq / 64, d3 = abs(b3 - wanted); 1191 1192 if (d1 < d2 && d1 < d3) { 1193 div = ZSWR4_CLK_X16; 1194 bps = b1; 1195 } else if (d2 < d3 && d2 < d1) { 1196 div = ZSWR4_CLK_X32; 1197 bps = b2; 1198 } else { 1199 div = ZSWR4_CLK_X64; 1200 bps = b3; 1201 } 1202 brgm = tcon = 0; 1203 break; 1204 } 1205 } 1206 diff = abs(bps - wanted); 1207 if (!source || diff < bestdiff) { 1208 *divisor = div; 1209 *clockmode = clkm; 1210 *brgenmode = brgm; 1211 *timeconst = tcon; 1212 bestbps = bps; 1213 bestdiff = diff; 1214 if (diff == 0) 1215 break; 1216 } 1217 } 1218 /* Allow deviations upto 5% */ 1219 if (20 * bestdiff > wanted) 1220 return -1; 1221 return bestbps; 1222 } 1223 1224 /* 1225 * Raise or lower modem control (DTR/RTS) signals. If a character is 1226 * in transmission, the change is deferred. 1227 */ 1228 static int 1229 zs_modem(cs, bits, how) 1230 struct zs_chanstate *cs; 1231 int bits, how; 1232 { 1233 int s, mbits; 1234 1235 bits &= ZSWR5_DTR | ZSWR5_RTS; 1236 1237 s = splzs(); 1238 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1239 1240 switch(how) { 1241 case DMSET: 1242 mbits = bits; 1243 break; 1244 case DMBIS: 1245 mbits |= bits; 1246 break; 1247 case DMBIC: 1248 mbits &= ~bits; 1249 break; 1250 case DMGET: 1251 splx(s); 1252 return(mbits); 1253 } 1254 1255 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1256 if(cs->cs_heldchange == 0) { 1257 if(cs->cs_ttyp->t_state & TS_BUSY) { 1258 cs->cs_heldtbc = cs->cs_tbc; 1259 cs->cs_tbc = 0; 1260 cs->cs_heldchange = 1; 1261 } 1262 else { 1263 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1264 } 1265 } 1266 splx(s); 1267 return(0); 1268 } 1269 1270 /* 1271 * Write the given register set to the given zs channel in the proper order. 1272 * The channel must not be transmitting at the time. The receiver will 1273 * be disabled for the time it takes to write all the registers. 1274 */ 1275 static void 1276 zs_loadchannelregs(zc, reg) 1277 volatile struct zschan *zc; 1278 u_char *reg; 1279 { 1280 int i; 1281 1282 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1283 i = zc->zc_data; /* drain fifo */ 1284 i = zc->zc_data; 1285 i = zc->zc_data; 1286 ZS_WRITE(zc, 4, reg[4]); 1287 ZS_WRITE(zc, 10, reg[10]); 1288 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1289 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1290 ZS_WRITE(zc, 1, reg[1]); 1291 ZS_WRITE(zc, 9, reg[9]); 1292 ZS_WRITE(zc, 11, reg[11]); 1293 ZS_WRITE(zc, 12, reg[12]); 1294 ZS_WRITE(zc, 13, reg[13]); 1295 ZS_WRITE(zc, 14, reg[14]); 1296 ZS_WRITE(zc, 15, reg[15]); 1297 ZS_WRITE(zc, 3, reg[3]); 1298 ZS_WRITE(zc, 5, reg[5]); 1299 } 1300 #endif /* NZS > 1 */ 1301