1 /* $NetBSD: pxa2x0_intr.h,v 1.8 2005/12/24 22:45:34 perry Exp $ */ 2 3 /* Derived from i80321_intr.h */ 4 5 /* 6 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _PXA2X0_INTR_H_ 41 #define _PXA2X0_INTR_H_ 42 43 #define ARM_IRQ_HANDLER _C_LABEL(pxa2x0_irq_handler) 44 45 #ifndef _LOCORE 46 47 #include <arm/cpu.h> 48 #include <arm/armreg.h> 49 #include <arm/cpufunc.h> 50 #include <machine/atomic.h> 51 #include <machine/intr.h> 52 #include <arm/softintr.h> 53 54 #include <arm/xscale/pxa2x0reg.h> 55 56 vaddr_t pxaic_base; /* Shared with pxa2x0_irq.S */ 57 #define read_icu(offset) (*(volatile uint32_t *)(pxaic_base+(offset))) 58 #define write_icu(offset,value) \ 59 (*(volatile uint32_t *)(pxaic_base+(offset))=(value)) 60 61 extern volatile int current_spl_level; 62 extern volatile int intr_mask; 63 extern volatile int softint_pending; 64 extern int pxa2x0_imask[]; 65 void pxa2x0_do_pending(void); 66 67 /* 68 * Cotulla's integrated ICU doesn't have IRQ0..7, so 69 * we map software interrupts to bit 0..3 70 */ 71 #define SI_TO_IRQBIT(si) (1U<<(si)) 72 73 static inline void 74 pxa2x0_setipl(int new) 75 { 76 current_spl_level = new; 77 intr_mask = pxa2x0_imask[current_spl_level]; 78 write_icu( SAIPIC_MR, intr_mask ); 79 } 80 81 82 static inline void 83 pxa2x0_splx(int new) 84 { 85 int psw; 86 87 psw = disable_interrupts(I32_bit); 88 pxa2x0_setipl(new); 89 restore_interrupts(psw); 90 91 /* If there are software interrupts to process, do it. */ 92 if (softint_pending & intr_mask) 93 pxa2x0_do_pending(); 94 } 95 96 97 static inline int 98 pxa2x0_splraise(int ipl) 99 { 100 int old, psw; 101 102 old = current_spl_level; 103 if( ipl > current_spl_level ){ 104 psw = disable_interrupts(I32_bit); 105 pxa2x0_setipl(ipl); 106 restore_interrupts(psw); 107 } 108 109 return (old); 110 } 111 112 static inline int 113 pxa2x0_spllower(int ipl) 114 { 115 int old = current_spl_level; 116 int psw = disable_interrupts(I32_bit); 117 pxa2x0_splx(ipl); 118 restore_interrupts(psw); 119 return(old); 120 } 121 122 static inline void 123 pxa2x0_setsoftintr(int si) 124 { 125 atomic_set_bit( (u_int *)__UNVOLATILE(&softint_pending), 126 SI_TO_IRQBIT(si) ); 127 128 /* Process unmasked pending soft interrupts. */ 129 if ( softint_pending & intr_mask ) 130 pxa2x0_do_pending(); 131 } 132 133 134 /* 135 * An useful function for interrupt handlers. 136 * XXX: This shouldn't be here. 137 */ 138 static inline int 139 find_first_bit( uint32_t bits ) 140 { 141 int count; 142 143 /* since CLZ is available only on ARMv5, this isn't portable 144 * to all ARM CPUs. This file is for PXA2[15]0 processor. 145 */ 146 __asm( "clz %0, %1" : "=r" (count) : "r" (bits) ); 147 return 31-count; 148 } 149 150 151 int _splraise(int); 152 int _spllower(int); 153 void splx(int); 154 void _setsoftintr(int); 155 156 #if !defined(EVBARM_SPL_NOINLINE) 157 158 #define splx(new) pxa2x0_splx(new) 159 #define _spllower(ipl) pxa2x0_spllower(ipl) 160 #define _splraise(ipl) pxa2x0_splraise(ipl) 161 #define _setsoftintr(si) pxa2x0_setsoftintr(si) 162 163 #endif /* !EVBARM_SPL_NOINTR */ 164 165 /* 166 * This function *MUST* be called very early on in a port's 167 * initarm() function, before ANY spl*() functions are called. 168 * 169 * The parameter is the virtual address of the PXA2x0's Interrupt 170 * Controller registers. 171 */ 172 void pxa2x0_intr_bootstrap(vaddr_t); 173 174 void pxa2x0_irq_handler(void *); 175 void *pxa2x0_intr_establish(int irqno, int level, 176 int (*func)(void *), void *cookie); 177 void pxa2x0_update_intr_masks(int irqno, int level); 178 extern volatile int current_spl_level; 179 180 #endif /* ! _LOCORE */ 181 182 #endif /* _PXA2X0_INTR_H_ */ 183