1 /* $NetBSD: pxa2x0_intr.c,v 1.4 2003/06/16 20:00:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/lock.h> 47 48 #include <arm/xscale/pxa2x0reg.h> 49 #include <arm/xscale/pxa2x0var.h> 50 #include <arm/xscale/pxa2x0_intr.h> 51 #include <arm/sa11x0/sa11x0_var.h> 52 53 /* 54 * INTC autoconf glue 55 */ 56 static int pxaintc_match(struct device *, struct cfdata *, void *); 57 static void pxaintc_attach(struct device *, struct device *, void *); 58 59 CFATTACH_DECL(pxaintc, sizeof(struct device), 60 pxaintc_match, pxaintc_attach, NULL, NULL); 61 62 static int pxaintc_attached; 63 64 static int stray_interrupt(void *); 65 static void init_interrupt_masks(void); 66 67 /* 68 * interrupt dispatch table. 69 */ 70 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 71 struct intrhand { 72 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 73 int (*ih_func)(void *); /* handler */ 74 void *ih_arg; /* arg for handler */ 75 }; 76 #endif 77 78 static struct { 79 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 80 TAILQ_HEAD(,intrhand) list; 81 #else 82 pxa2x0_irq_handler_t func; 83 #endif 84 void *cookie; /* NULL for stackframe */ 85 /* struct evbnt ev; */ 86 } handler[ICU_LEN]; 87 88 __volatile int softint_pending; 89 __volatile int current_spl_level; 90 __volatile int intr_mask; 91 /* interrupt masks for each level */ 92 int pxa2x0_imask[NIPL]; 93 static int extirq_level[ICU_LEN]; 94 95 96 static int 97 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux) 98 { 99 struct pxaip_attach_args *pxa = aux; 100 101 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 102 return (0); 103 104 return (1); 105 } 106 107 void 108 pxaintc_attach(struct device *parent, struct device *self, void *args) 109 { 110 int i; 111 112 pxaintc_attached = 1; 113 114 aprint_normal(": Interrupt Controller\n"); 115 116 #define SAIPIC_ICCR 0x14 117 118 write_icu(SAIPIC_ICCR, 1); 119 write_icu(SAIPIC_MR, 0); 120 121 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 122 handler[i].func = stray_interrupt; 123 handler[i].cookie = (void *)(intptr_t) i; 124 extirq_level[i] = IPL_SERIAL; 125 } 126 127 init_interrupt_masks(); 128 129 _splraise(IPL_SERIAL); 130 enable_interrupts(I32_bit); 131 } 132 133 /* 134 * Invoked very early on from the board-specific initarm(), in order to 135 * inform us the virtual address of the interrupt controller's registers. 136 */ 137 void 138 pxa2x0_intr_bootstrap(vaddr_t addr) 139 { 140 141 pxaic_base = addr; 142 } 143 144 static __inline void 145 __raise(int ipl) 146 { 147 148 if (current_spl_level < ipl) 149 pxa2x0_setipl(ipl); 150 } 151 152 153 /* 154 * Map a software interrupt queue to an interrupt priority level. 155 */ 156 static const int si_to_ipl[SI_NQUEUES] = { 157 IPL_SOFT, /* SI_SOFT */ 158 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 159 IPL_SOFTNET, /* SI_SOFTNET */ 160 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 161 }; 162 163 /* 164 * called from irq_entry. 165 */ 166 void 167 pxa2x0_irq_handler(void *arg) 168 { 169 struct clockframe *frame = arg; 170 uint32_t irqbits; 171 int irqno; 172 int saved_spl_level; 173 174 saved_spl_level = current_spl_level; 175 176 /* get pending IRQs */ 177 irqbits = read_icu(SAIPIC_IP); 178 179 while ((irqno = find_first_bit(irqbits)) >= 0) { 180 /* XXX: Shuould we handle IRQs in priority order? */ 181 182 /* raise spl to stop interrupts of lower priorities */ 183 if (saved_spl_level < extirq_level[irqno]) 184 pxa2x0_setipl(extirq_level[irqno]); 185 186 #ifdef notyet 187 /* Enable interrupt */ 188 #endif 189 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 190 (* handler[irqno].func)( 191 handler[irqno].cookie == 0 192 ? frame : handler[irqno].cookie ); 193 #else 194 /* process all handlers for this interrupt. 195 XXX not yet */ 196 #endif 197 198 #ifdef notyet 199 /* Disable interrupt */ 200 #endif 201 202 irqbits &= ~(1<<irqno); 203 } 204 205 /* restore spl to that was when this interrupt happen */ 206 pxa2x0_setipl(saved_spl_level); 207 208 if(softint_pending & intr_mask) 209 pxa2x0_do_pending(); 210 } 211 212 static int 213 stray_interrupt(void *cookie) 214 { 215 int irqno = (int)cookie; 216 printf("stray interrupt %d\n", irqno); 217 218 if (PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN){ 219 int save = disable_interrupts(I32_bit); 220 write_icu(SAIPIC_MR, 221 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 222 restore_interrupts(save); 223 } 224 225 return 0; 226 } 227 228 229 230 /* 231 * Interrupt Mask Handling 232 */ 233 234 void 235 pxa2x0_update_intr_masks(int irqno, int level) 236 { 237 int mask = 1U<<irqno; 238 int psw = disable_interrupts(I32_bit); 239 int i; 240 241 for(i = 0; i < level; ++i) 242 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 243 244 for( ; i < NIPL-1; ++i) 245 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */ 246 247 /* 248 * Enforce a heirarchy that gives "slow" device (or devices with 249 * limited input buffer space/"real-time" requirements) a better 250 * chance at not dropping data. 251 */ 252 pxa2x0_imask[IPL_BIO] &= pxa2x0_imask[IPL_SOFTNET]; 253 pxa2x0_imask[IPL_NET] &= pxa2x0_imask[IPL_BIO]; 254 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_NET]; 255 pxa2x0_imask[IPL_TTY] &= pxa2x0_imask[IPL_SOFTSERIAL]; 256 257 /* 258 * splvm() blocks all interrupts that use the kernel memory 259 * allocation facilities. 260 */ 261 pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_TTY]; 262 263 /* 264 * Audio devices are not allowed to perform memory allocation 265 * in their interrupt routines, and they have fairly "real-time" 266 * requirements, so give them a high interrupt priority. 267 */ 268 pxa2x0_imask[IPL_AUDIO] &= pxa2x0_imask[IPL_VM]; 269 270 /* 271 * splclock() must block anything that uses the scheduler. 272 */ 273 pxa2x0_imask[IPL_CLOCK] &= pxa2x0_imask[IPL_AUDIO]; 274 275 /* 276 * splhigh() must block "everything". 277 */ 278 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_STATCLOCK]; 279 280 /* 281 * XXX We need serial drivers to run at the absolute highest priority 282 * in order to avoid overruns, so serial > high. 283 */ 284 pxa2x0_imask[IPL_SERIAL] &= pxa2x0_imask[IPL_HIGH]; 285 286 write_icu(SAIPIC_MR, pxa2x0_imask[current_spl_level]); 287 288 restore_interrupts(psw); 289 } 290 291 292 static void 293 init_interrupt_masks(void) 294 { 295 296 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 297 298 /* 299 * IPL_NONE has soft interrupts enabled only, at least until 300 * hardware handlers are installed. 301 */ 302 pxa2x0_imask[IPL_NONE] = 303 SI_TO_IRQBIT(SI_SOFT) | 304 SI_TO_IRQBIT(SI_SOFTCLOCK) | 305 SI_TO_IRQBIT(SI_SOFTNET) | 306 SI_TO_IRQBIT(SI_SOFTSERIAL); 307 308 /* 309 * Initialize the soft interrupt masks to block themselves. 310 */ 311 pxa2x0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT); 312 pxa2x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 313 pxa2x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 314 pxa2x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL); 315 316 pxa2x0_imask[IPL_SOFT] &= pxa2x0_imask[IPL_NONE]; 317 318 /* 319 * splsoftclock() is the only interface that users of the 320 * generic software interrupt facility have to block their 321 * soft intrs, so splsoftclock() must also block IPL_SOFT. 322 */ 323 pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_SOFT]; 324 325 /* 326 * splsoftnet() must also block splsoftclock(), since we don't 327 * want timer-driven network events to occur while we're 328 * processing incoming packets. 329 */ 330 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTCLOCK]; 331 } 332 333 void 334 pxa2x0_do_pending(void) 335 { 336 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 337 int oldirqstate, spl_save; 338 339 if (__cpu_simple_lock_try(&processing) == 0) 340 return; 341 342 spl_save = current_spl_level; 343 344 oldirqstate = disable_interrupts(I32_bit); 345 346 #if 1 347 #define DO_SOFTINT(si,ipl) \ 348 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 349 softint_pending &= ~SI_TO_IRQBIT(si); \ 350 __raise(ipl); \ 351 restore_interrupts(oldirqstate); \ 352 softintr_dispatch(si); \ 353 oldirqstate = disable_interrupts(I32_bit); \ 354 pxa2x0_setipl(spl_save); \ 355 } 356 357 do { 358 DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL); 359 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 360 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 361 DO_SOFTINT(SI_SOFT, IPL_SOFT); 362 } while( softint_pending & intr_mask ); 363 #else 364 while( (si = find_first_bit(softint_pending & intr_mask)) >= 0 ){ 365 softint_pending &= ~SI_TO_IRQBIT(si); 366 __raise(si_to_ipl(si)); 367 restore_interrupts(oldirqstate); 368 softintr_dispatch(si); 369 oldirqstate = disable_interrupts(I32_bit); 370 pxa2x0_setipl(spl_save); 371 } 372 #endif 373 374 __cpu_simple_unlock(&processing); 375 376 restore_interrupts(oldirqstate); 377 } 378 379 380 #undef splx 381 void 382 splx(int ipl) 383 { 384 385 pxa2x0_splx(ipl); 386 } 387 388 #undef _splraise 389 int 390 _splraise(int ipl) 391 { 392 393 return pxa2x0_splraise(ipl); 394 } 395 396 #undef _spllower 397 int 398 _spllower(int ipl) 399 { 400 401 return pxa2x0_spllower(ipl); 402 } 403 404 #undef _setsoftintr 405 void 406 _setsoftintr(int si) 407 { 408 409 return pxa2x0_setsoftintr(si); 410 } 411 412 void * 413 pxa2x0_intr_establish(int irqno, int level, 414 int (*func)(void *), void *cookie) 415 { 416 int psw; 417 418 if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN) 419 panic("intr_establish: bogus irq number %d", irqno); 420 421 psw = disable_interrupts(I32_bit); 422 423 handler[irqno].cookie = cookie; 424 handler[irqno].func = func; 425 extirq_level[irqno] = level; 426 pxa2x0_update_intr_masks(irqno, level); 427 428 intr_mask = pxa2x0_imask[current_spl_level]; 429 430 restore_interrupts(psw); 431 432 return (&handler[irqno]); 433 } 434 435 /* 436 * Glue for drivers of sa11x0 compatible integrated logics. 437 */ 438 void * 439 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 440 int (*ih_fun)(void *), void *ih_arg) 441 { 442 443 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 444 } 445