1 /* $NetBSD: pxa2x0_intr.c,v 1.8 2005/12/24 20:06:52 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.8 2005/12/24 20:06:52 perry Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(struct device *, struct cfdata *, void *); 62 static void pxaintc_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(pxaintc, sizeof(struct device), 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 volatile int softint_pending; 94 volatile int current_spl_level; 95 volatile int intr_mask; 96 /* interrupt masks for each level */ 97 int pxa2x0_imask[NIPL]; 98 static int extirq_level[ICU_LEN]; 99 100 101 static int 102 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux) 103 { 104 struct pxaip_attach_args *pxa = aux; 105 106 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 107 return (0); 108 109 return (1); 110 } 111 112 void 113 pxaintc_attach(struct device *parent, struct device *self, void *args) 114 { 115 int i; 116 117 pxaintc_attached = 1; 118 119 aprint_normal(": Interrupt Controller\n"); 120 121 #define SAIPIC_ICCR 0x14 122 123 write_icu(SAIPIC_ICCR, 1); 124 write_icu(SAIPIC_MR, 0); 125 126 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 127 handler[i].func = stray_interrupt; 128 handler[i].cookie = (void *)(intptr_t) i; 129 extirq_level[i] = IPL_SERIAL; 130 } 131 132 init_interrupt_masks(); 133 134 _splraise(IPL_SERIAL); 135 enable_interrupts(I32_bit); 136 } 137 138 /* 139 * Invoked very early on from the board-specific initarm(), in order to 140 * inform us the virtual address of the interrupt controller's registers. 141 */ 142 void 143 pxa2x0_intr_bootstrap(vaddr_t addr) 144 { 145 146 pxaic_base = addr; 147 } 148 149 static inline void 150 __raise(int ipl) 151 { 152 153 if (current_spl_level < ipl) 154 pxa2x0_setipl(ipl); 155 } 156 157 158 /* 159 * Map a software interrupt queue to an interrupt priority level. 160 */ 161 static const int si_to_ipl[SI_NQUEUES] = { 162 IPL_SOFT, /* SI_SOFT */ 163 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 164 IPL_SOFTNET, /* SI_SOFTNET */ 165 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 166 }; 167 168 /* 169 * called from irq_entry. 170 */ 171 void 172 pxa2x0_irq_handler(void *arg) 173 { 174 struct clockframe *frame = arg; 175 uint32_t irqbits; 176 int irqno; 177 int saved_spl_level; 178 179 saved_spl_level = current_spl_level; 180 181 /* get pending IRQs */ 182 irqbits = read_icu(SAIPIC_IP); 183 184 while ((irqno = find_first_bit(irqbits)) >= 0) { 185 /* XXX: Shuould we handle IRQs in priority order? */ 186 187 /* raise spl to stop interrupts of lower priorities */ 188 if (saved_spl_level < extirq_level[irqno]) 189 pxa2x0_setipl(extirq_level[irqno]); 190 191 #ifdef notyet 192 /* Enable interrupt */ 193 #endif 194 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 195 (* handler[irqno].func)( 196 handler[irqno].cookie == 0 197 ? frame : handler[irqno].cookie ); 198 #else 199 /* process all handlers for this interrupt. 200 XXX not yet */ 201 #endif 202 203 #ifdef notyet 204 /* Disable interrupt */ 205 #endif 206 207 irqbits &= ~(1<<irqno); 208 } 209 210 /* restore spl to that was when this interrupt happen */ 211 pxa2x0_setipl(saved_spl_level); 212 213 if(softint_pending & intr_mask) 214 pxa2x0_do_pending(); 215 } 216 217 static int 218 stray_interrupt(void *cookie) 219 { 220 int irqno = (int)cookie; 221 printf("stray interrupt %d\n", irqno); 222 223 if (PXA270_IRQ_MIN <= irqno && irqno < ICU_LEN){ 224 int save = disable_interrupts(I32_bit); 225 write_icu(SAIPIC_MR, 226 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 227 restore_interrupts(save); 228 } 229 230 return 0; 231 } 232 233 234 235 /* 236 * Interrupt Mask Handling 237 */ 238 239 void 240 pxa2x0_update_intr_masks(int irqno, int level) 241 { 242 int mask = 1U<<irqno; 243 int psw = disable_interrupts(I32_bit); 244 int i; 245 246 for(i = 0; i < level; ++i) 247 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 248 249 for( ; i < NIPL-1; ++i) 250 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */ 251 252 /* 253 * Enforce a heirarchy that gives "slow" device (or devices with 254 * limited input buffer space/"real-time" requirements) a better 255 * chance at not dropping data. 256 */ 257 pxa2x0_imask[IPL_BIO] &= pxa2x0_imask[IPL_SOFTNET]; 258 pxa2x0_imask[IPL_NET] &= pxa2x0_imask[IPL_BIO]; 259 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_NET]; 260 pxa2x0_imask[IPL_TTY] &= pxa2x0_imask[IPL_SOFTSERIAL]; 261 262 /* 263 * splvm() blocks all interrupts that use the kernel memory 264 * allocation facilities. 265 */ 266 pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_TTY]; 267 268 /* 269 * Audio devices are not allowed to perform memory allocation 270 * in their interrupt routines, and they have fairly "real-time" 271 * requirements, so give them a high interrupt priority. 272 */ 273 pxa2x0_imask[IPL_AUDIO] &= pxa2x0_imask[IPL_VM]; 274 275 /* 276 * splclock() must block anything that uses the scheduler. 277 */ 278 pxa2x0_imask[IPL_CLOCK] &= pxa2x0_imask[IPL_AUDIO]; 279 280 /* 281 * splhigh() must block "everything". 282 */ 283 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_STATCLOCK]; 284 285 /* 286 * XXX We need serial drivers to run at the absolute highest priority 287 * in order to avoid overruns, so serial > high. 288 */ 289 pxa2x0_imask[IPL_SERIAL] &= pxa2x0_imask[IPL_HIGH]; 290 291 write_icu(SAIPIC_MR, pxa2x0_imask[current_spl_level]); 292 293 restore_interrupts(psw); 294 } 295 296 297 static void 298 init_interrupt_masks(void) 299 { 300 301 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 302 303 /* 304 * IPL_NONE has soft interrupts enabled only, at least until 305 * hardware handlers are installed. 306 */ 307 pxa2x0_imask[IPL_NONE] = 308 SI_TO_IRQBIT(SI_SOFT) | 309 SI_TO_IRQBIT(SI_SOFTCLOCK) | 310 SI_TO_IRQBIT(SI_SOFTNET) | 311 SI_TO_IRQBIT(SI_SOFTSERIAL); 312 313 /* 314 * Initialize the soft interrupt masks to block themselves. 315 */ 316 pxa2x0_imask[IPL_SOFT] = ~SI_TO_IRQBIT(SI_SOFT); 317 pxa2x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 318 pxa2x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 319 pxa2x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL); 320 321 pxa2x0_imask[IPL_SOFT] &= pxa2x0_imask[IPL_NONE]; 322 323 /* 324 * splsoftclock() is the only interface that users of the 325 * generic software interrupt facility have to block their 326 * soft intrs, so splsoftclock() must also block IPL_SOFT. 327 */ 328 pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_SOFT]; 329 330 /* 331 * splsoftnet() must also block splsoftclock(), since we don't 332 * want timer-driven network events to occur while we're 333 * processing incoming packets. 334 */ 335 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTCLOCK]; 336 } 337 338 void 339 pxa2x0_do_pending(void) 340 { 341 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 342 int oldirqstate, spl_save; 343 344 if (__cpu_simple_lock_try(&processing) == 0) 345 return; 346 347 spl_save = current_spl_level; 348 349 oldirqstate = disable_interrupts(I32_bit); 350 351 #if 1 352 #define DO_SOFTINT(si,ipl) \ 353 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 354 softint_pending &= ~SI_TO_IRQBIT(si); \ 355 __raise(ipl); \ 356 restore_interrupts(oldirqstate); \ 357 softintr_dispatch(si); \ 358 oldirqstate = disable_interrupts(I32_bit); \ 359 pxa2x0_setipl(spl_save); \ 360 } 361 362 do { 363 DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL); 364 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 365 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 366 DO_SOFTINT(SI_SOFT, IPL_SOFT); 367 } while( softint_pending & intr_mask ); 368 #else 369 while( (si = find_first_bit(softint_pending & intr_mask)) >= 0 ){ 370 softint_pending &= ~SI_TO_IRQBIT(si); 371 __raise(si_to_ipl(si)); 372 restore_interrupts(oldirqstate); 373 softintr_dispatch(si); 374 oldirqstate = disable_interrupts(I32_bit); 375 pxa2x0_setipl(spl_save); 376 } 377 #endif 378 379 __cpu_simple_unlock(&processing); 380 381 restore_interrupts(oldirqstate); 382 } 383 384 385 #undef splx 386 void 387 splx(int ipl) 388 { 389 390 pxa2x0_splx(ipl); 391 } 392 393 #undef _splraise 394 int 395 _splraise(int ipl) 396 { 397 398 return pxa2x0_splraise(ipl); 399 } 400 401 #undef _spllower 402 int 403 _spllower(int ipl) 404 { 405 406 return pxa2x0_spllower(ipl); 407 } 408 409 #undef _setsoftintr 410 void 411 _setsoftintr(int si) 412 { 413 414 return pxa2x0_setsoftintr(si); 415 } 416 417 void * 418 pxa2x0_intr_establish(int irqno, int level, 419 int (*func)(void *), void *cookie) 420 { 421 int psw; 422 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 423 424 if (irqno < irqmin || irqno >= ICU_LEN) 425 panic("intr_establish: bogus irq number %d", irqno); 426 427 psw = disable_interrupts(I32_bit); 428 429 handler[irqno].cookie = cookie; 430 handler[irqno].func = func; 431 extirq_level[irqno] = level; 432 pxa2x0_update_intr_masks(irqno, level); 433 434 intr_mask = pxa2x0_imask[current_spl_level]; 435 436 restore_interrupts(psw); 437 438 return (&handler[irqno]); 439 } 440 441 /* 442 * Glue for drivers of sa11x0 compatible integrated logics. 443 */ 444 void * 445 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 446 int (*ih_fun)(void *), void *ih_arg) 447 { 448 449 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 450 } 451