1 /* $NetBSD: pxa2x0_intr.c,v 1.13 2007/12/11 17:12:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.13 2007/12/11 17:12:27 ad Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(struct device *, struct cfdata *, void *); 62 static void pxaintc_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(pxaintc, sizeof(struct device), 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct intrhandler { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 volatile int softint_pending; 94 volatile int current_spl_level; 95 volatile int intr_mask; 96 /* interrupt masks for each level */ 97 int pxa2x0_imask[NIPL]; 98 static int extirq_level[ICU_LEN]; 99 100 101 static int 102 pxaintc_match(struct device *parent, struct cfdata *cf, void *aux) 103 { 104 struct pxaip_attach_args *pxa = aux; 105 106 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 107 return (0); 108 109 return (1); 110 } 111 112 void 113 pxaintc_attach(struct device *parent, struct device *self, void *args) 114 { 115 int i; 116 117 pxaintc_attached = 1; 118 119 aprint_normal(": Interrupt Controller\n"); 120 121 #define SAIPIC_ICCR 0x14 122 123 write_icu(SAIPIC_ICCR, 1); 124 write_icu(SAIPIC_MR, 0); 125 126 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 127 handler[i].func = stray_interrupt; 128 handler[i].cookie = (void *)(intptr_t) i; 129 extirq_level[i] = IPL_SERIAL; 130 } 131 132 init_interrupt_masks(); 133 134 _splraise(IPL_SERIAL); 135 enable_interrupts(I32_bit); 136 } 137 138 /* 139 * Invoked very early on from the board-specific initarm(), in order to 140 * inform us the virtual address of the interrupt controller's registers. 141 */ 142 void 143 pxa2x0_intr_bootstrap(vaddr_t addr) 144 { 145 146 pxaic_base = addr; 147 } 148 149 static inline void 150 __raise(int ipl) 151 { 152 153 if (current_spl_level < ipl) 154 pxa2x0_setipl(ipl); 155 } 156 157 158 /* 159 * Map a software interrupt queue to an interrupt priority level. 160 */ 161 static const int si_to_ipl[SI_NQUEUES] = { 162 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 163 IPL_SOFTBIO, /* SI_SOFTBIO */ 164 IPL_SOFTNET, /* SI_SOFTNET */ 165 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 166 }; 167 168 /* 169 * called from irq_entry. 170 */ 171 void 172 pxa2x0_irq_handler(void *arg) 173 { 174 struct clockframe *frame = arg; 175 uint32_t irqbits; 176 int irqno; 177 int saved_spl_level; 178 struct cpu_info *ci; 179 180 ci = curcpu(); 181 ci->ci_idepth++; 182 saved_spl_level = current_spl_level; 183 184 /* get pending IRQs */ 185 irqbits = read_icu(SAIPIC_IP); 186 187 while ((irqno = find_first_bit(irqbits)) >= 0) { 188 /* XXX: Shuould we handle IRQs in priority order? */ 189 190 /* raise spl to stop interrupts of lower priorities */ 191 if (saved_spl_level < extirq_level[irqno]) 192 pxa2x0_setipl(extirq_level[irqno]); 193 194 #ifdef notyet 195 /* Enable interrupt */ 196 #endif 197 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 198 (* handler[irqno].func)( 199 handler[irqno].cookie == 0 200 ? frame : handler[irqno].cookie ); 201 #else 202 /* process all handlers for this interrupt. 203 XXX not yet */ 204 #endif 205 206 #ifdef notyet 207 /* Disable interrupt */ 208 #endif 209 210 irqbits &= ~(1<<irqno); 211 } 212 213 /* restore spl to that was when this interrupt happen */ 214 pxa2x0_setipl(saved_spl_level); 215 216 ci->ci_idepth--; 217 218 if(softint_pending & intr_mask) 219 pxa2x0_do_pending(); 220 } 221 222 static int 223 stray_interrupt(void *cookie) 224 { 225 int irqno = (int)cookie; 226 printf("stray interrupt %d\n", irqno); 227 228 if (PXA270_IRQ_MIN <= irqno && irqno < ICU_LEN){ 229 int save = disable_interrupts(I32_bit); 230 write_icu(SAIPIC_MR, 231 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 232 restore_interrupts(save); 233 } 234 235 return 0; 236 } 237 238 239 240 /* 241 * Interrupt Mask Handling 242 */ 243 244 void 245 pxa2x0_update_intr_masks(int irqno, int level) 246 { 247 int mask = 1U<<irqno; 248 int psw = disable_interrupts(I32_bit); 249 int i; 250 251 for(i = 0; i < level; ++i) 252 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 253 254 for( ; i < NIPL-1; ++i) 255 pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */ 256 257 /* 258 * Enforce a hierarchy that gives "slow" device (or devices with 259 * limited input buffer space/"real-time" requirements) a better 260 * chance at not dropping data. 261 */ 262 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 263 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 264 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 265 pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL]; 266 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 267 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 268 269 write_icu(SAIPIC_MR, pxa2x0_imask[current_spl_level]); 270 271 restore_interrupts(psw); 272 } 273 274 275 static void 276 init_interrupt_masks(void) 277 { 278 279 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 280 281 /* 282 * IPL_NONE has soft interrupts enabled only, at least until 283 * hardware handlers are installed. 284 */ 285 pxa2x0_imask[IPL_NONE] = 286 SI_TO_IRQBIT(SI_SOFTCLOCK) | 287 SI_TO_IRQBIT(SI_SOFTBIO) | 288 SI_TO_IRQBIT(SI_SOFTNET) | 289 SI_TO_IRQBIT(SI_SOFTSERIAL); 290 291 /* 292 * Initialize the soft interrupt masks to block themselves. 293 */ 294 pxa2x0_imask[IPL_SOFTCLOCK] = ~SI_TO_IRQBIT(SI_SOFTCLOCK); 295 pxa2x0_imask[IPL_SOFTBIO] = ~SI_TO_IRQBIT(SI_SOFTBIO); 296 pxa2x0_imask[IPL_SOFTNET] = ~SI_TO_IRQBIT(SI_SOFTNET); 297 pxa2x0_imask[IPL_SOFTSERIAL] = ~SI_TO_IRQBIT(SI_SOFTSERIAL); 298 299 pxa2x0_imask[IPL_SOFTCLOCK] &= pxa2x0_imask[IPL_NONE]; 300 pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK]; 301 pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO]; 302 pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET]; 303 } 304 305 void 306 pxa2x0_do_pending(void) 307 { 308 #ifdef __HAVE_FAST_SOFTINTS 309 static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED; 310 int oldirqstate, spl_save; 311 312 if (__cpu_simple_lock_try(&processing) == 0) 313 return; 314 315 spl_save = current_spl_level; 316 317 oldirqstate = disable_interrupts(I32_bit); 318 319 #if 1 320 #define DO_SOFTINT(si,ipl) \ 321 if ((softint_pending & intr_mask) & SI_TO_IRQBIT(si)) { \ 322 softint_pending &= ~SI_TO_IRQBIT(si); \ 323 __raise(ipl); \ 324 restore_interrupts(oldirqstate); \ 325 softintr_dispatch(si); \ 326 oldirqstate = disable_interrupts(I32_bit); \ 327 pxa2x0_setipl(spl_save); \ 328 } 329 330 do { 331 DO_SOFTINT(SI_SOFTSERIAL,IPL_SOFTSERIAL); 332 DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET); 333 DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK); 334 DO_SOFTINT(SI_SOFT, IPL_SOFT); 335 } while( softint_pending & intr_mask ); 336 #else 337 while( (si = find_first_bit(softint_pending & intr_mask)) >= 0 ){ 338 softint_pending &= ~SI_TO_IRQBIT(si); 339 __raise(si_to_ipl(si)); 340 restore_interrupts(oldirqstate); 341 softintr_dispatch(si); 342 oldirqstate = disable_interrupts(I32_bit); 343 pxa2x0_setipl(spl_save); 344 } 345 #endif 346 347 __cpu_simple_unlock(&processing); 348 349 restore_interrupts(oldirqstate); 350 #endif 351 } 352 353 354 #undef splx 355 void 356 splx(int ipl) 357 { 358 359 pxa2x0_splx(ipl); 360 } 361 362 #undef _splraise 363 int 364 _splraise(int ipl) 365 { 366 367 return pxa2x0_splraise(ipl); 368 } 369 370 #undef _spllower 371 int 372 _spllower(int ipl) 373 { 374 375 return pxa2x0_spllower(ipl); 376 } 377 378 #undef _setsoftintr 379 void 380 _setsoftintr(int si) 381 { 382 383 return pxa2x0_setsoftintr(si); 384 } 385 386 void * 387 pxa2x0_intr_establish(int irqno, int level, 388 int (*func)(void *), void *cookie) 389 { 390 int psw; 391 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 392 393 if (irqno < irqmin || irqno >= ICU_LEN) 394 panic("intr_establish: bogus irq number %d", irqno); 395 396 psw = disable_interrupts(I32_bit); 397 398 handler[irqno].cookie = cookie; 399 handler[irqno].func = func; 400 extirq_level[irqno] = level; 401 pxa2x0_update_intr_masks(irqno, level); 402 403 intr_mask = pxa2x0_imask[current_spl_level]; 404 405 restore_interrupts(psw); 406 407 return (&handler[irqno]); 408 } 409 410 void 411 pxa2x0_intr_disestablish(void *cookie) 412 { 413 struct intrhandler *lhandler = cookie, *ih; 414 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 415 int irqno = lhandler - handler; 416 int psw; 417 418 if (irqno < irqmin || irqno >= ICU_LEN) 419 panic("intr_disestablish: bogus irq number %d", irqno); 420 421 psw = disable_interrupts(I32_bit); 422 423 ih = &handler[irqno]; 424 ih->func = stray_interrupt; 425 ih->cookie = (void *)(intptr_t)irqno; 426 extirq_level[irqno] = IPL_SERIAL; 427 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 428 429 restore_interrupts(psw); 430 } 431 432 /* 433 * Glue for drivers of sa11x0 compatible integrated logics. 434 */ 435 void * 436 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 437 int (*ih_fun)(void *), void *ih_arg) 438 { 439 440 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 441 } 442