1 /* $NetBSD: pxa2x0_intr.c,v 1.23 2021/01/04 15:13:50 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.23 2021/01/04 15:13:50 skrll Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <sys/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(device_t, cfdata_t, void *); 62 static void pxaintc_attach(device_t, device_t, void *); 63 64 CFATTACH_DECL_NEW(pxaintc, 0, 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct intrhandler { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 vaddr_t pxaic_base; 94 volatile int softint_pending; 95 volatile int intr_mask; 96 /* interrupt masks for each level */ 97 int pxa2x0_imask[NIPL]; 98 static int extirq_level[ICU_LEN]; 99 100 101 static int 102 pxaintc_match(device_t parent, cfdata_t cf, void *aux) 103 { 104 struct pxaip_attach_args *pxa = aux; 105 106 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 107 return (0); 108 109 return (1); 110 } 111 112 void 113 pxaintc_attach(device_t parent, device_t self, void *args) 114 { 115 int i; 116 117 pxaintc_attached = 1; 118 119 aprint_normal(": Interrupt Controller\n"); 120 121 #define SAIPIC_ICCR 0x14 122 123 write_icu(SAIPIC_ICCR, 1); 124 write_icu(SAIPIC_MR, 0); 125 126 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 127 handler[i].func = stray_interrupt; 128 handler[i].cookie = (void *)(intptr_t) i; 129 extirq_level[i] = IPL_SERIAL; 130 } 131 132 init_interrupt_masks(); 133 134 _splraise(IPL_SERIAL); 135 enable_interrupts(I32_bit); 136 } 137 138 /* 139 * Invoked very early on from the board-specific initarm(), in order to 140 * inform us the virtual address of the interrupt controller's registers. 141 */ 142 void 143 pxa2x0_intr_bootstrap(vaddr_t addr) 144 { 145 146 pxaic_base = addr; 147 } 148 149 /* 150 * called from irq_entry. 151 */ 152 void 153 pxa2x0_irq_handler(void *arg) 154 { 155 struct clockframe *frame = arg; 156 uint32_t irqbits; 157 int irqno; 158 int saved_spl_level; 159 160 saved_spl_level = curcpu()->ci_cpl; 161 162 /* get pending IRQs */ 163 irqbits = read_icu(SAIPIC_IP); 164 165 while ((irqno = find_first_bit(irqbits)) >= 0) { 166 /* XXX: Shuould we handle IRQs in priority order? */ 167 168 /* raise spl to stop interrupts of lower priorities */ 169 if (saved_spl_level < extirq_level[irqno]) 170 pxa2x0_setipl(extirq_level[irqno]); 171 172 #ifdef notyet 173 /* Enable interrupt */ 174 #endif 175 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 176 (* handler[irqno].func)( 177 handler[irqno].cookie == 0 178 ? frame : handler[irqno].cookie ); 179 #else 180 /* process all handlers for this interrupt. 181 XXX not yet */ 182 #endif 183 184 #ifdef notyet 185 /* Disable interrupt */ 186 #endif 187 188 irqbits &= ~(1<<irqno); 189 } 190 191 /* restore spl to that was when this interrupt happen */ 192 pxa2x0_setipl(saved_spl_level); 193 194 #ifdef __HAVE_FAST_SOFTINTS 195 cpu_dosoftints(); 196 #endif 197 } 198 199 static int 200 stray_interrupt(void *cookie) 201 { 202 int irqno = (int)cookie; 203 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 204 205 printf("stray interrupt %d\n", irqno); 206 207 if (irqmin <= irqno && irqno < ICU_LEN){ 208 int save = disable_interrupts(I32_bit); 209 write_icu(SAIPIC_MR, 210 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 211 restore_interrupts(save); 212 } 213 214 return 0; 215 } 216 217 218 219 /* 220 * Interrupt Mask Handling 221 */ 222 223 void 224 pxa2x0_update_intr_masks(int irqno, int level) 225 { 226 int mask = 1U<<irqno; 227 int psw = disable_interrupts(I32_bit); 228 int i; 229 230 for(i = 0; i < level; ++i) 231 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 232 233 for( ; i < NIPL-1; ++i) 234 pxa2x0_imask[i] &= ~mask; /* Disable interrupt at upper level */ 235 236 /* 237 * Enforce a hierarchy that gives "slow" device (or devices with 238 * limited input buffer space/"real-time" requirements) a better 239 * chance at not dropping data. 240 */ 241 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 242 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 243 244 write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]); 245 246 restore_interrupts(psw); 247 } 248 249 250 static void 251 init_interrupt_masks(void) 252 { 253 254 /* 255 * disable all interrupts until handlers are installed. 256 */ 257 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 258 259 } 260 261 #undef splx 262 void 263 splx(int ipl) 264 { 265 pxa2x0_splx(ipl); 266 } 267 268 #undef _splraise 269 int 270 _splraise(int ipl) 271 { 272 return pxa2x0_splraise(ipl); 273 } 274 275 #undef _spllower 276 int 277 _spllower(int ipl) 278 { 279 return pxa2x0_spllower(ipl); 280 } 281 282 void * 283 pxa2x0_intr_establish(int irqno, int level, 284 int (*func)(void *), void *cookie) 285 { 286 int psw; 287 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 288 289 if (irqno < irqmin || irqno >= ICU_LEN) 290 panic("intr_establish: bogus irq number %d", irqno); 291 292 psw = disable_interrupts(I32_bit); 293 294 handler[irqno].cookie = cookie; 295 handler[irqno].func = func; 296 extirq_level[irqno] = level; 297 pxa2x0_update_intr_masks(irqno, level); 298 299 intr_mask = pxa2x0_imask[curcpu()->ci_cpl]; 300 301 restore_interrupts(psw); 302 303 return (&handler[irqno]); 304 } 305 306 void 307 pxa2x0_intr_disestablish(void *cookie) 308 { 309 struct intrhandler *lhandler = cookie, *ih; 310 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 311 int irqno = lhandler - handler; 312 int psw; 313 314 if (irqno < irqmin || irqno >= ICU_LEN) 315 panic("intr_disestablish: bogus irq number %d", irqno); 316 317 psw = disable_interrupts(I32_bit); 318 319 ih = &handler[irqno]; 320 ih->func = stray_interrupt; 321 ih->cookie = (void *)(intptr_t)irqno; 322 extirq_level[irqno] = IPL_SERIAL; 323 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 324 325 restore_interrupts(psw); 326 } 327 328 /* 329 * Glue for drivers of sa11x0 compatible integrated logics. 330 */ 331 void * 332 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 333 int (*ih_fun)(void *), void *ih_arg) 334 { 335 336 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 337 } 338