1 /* $NetBSD: pxa2x0_intr.c,v 1.25 2022/10/31 21:22:05 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.25 2022/10/31 21:22:05 andvar Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 #include <machine/lock.h> 50 51 #include <arm/xscale/pxa2x0cpu.h> 52 #include <arm/xscale/pxa2x0reg.h> 53 #include <arm/xscale/pxa2x0var.h> 54 #include <arm/xscale/pxa2x0_intr.h> 55 #include <arm/sa11x0/sa11x0_var.h> 56 57 /* 58 * INTC autoconf glue 59 */ 60 static int pxaintc_match(device_t, cfdata_t, void *); 61 static void pxaintc_attach(device_t, device_t, void *); 62 63 CFATTACH_DECL_NEW(pxaintc, 0, 64 pxaintc_match, pxaintc_attach, NULL, NULL); 65 66 static int pxaintc_attached; 67 68 static int stray_interrupt(void *); 69 static void init_interrupt_masks(void); 70 71 /* 72 * interrupt dispatch table. 73 */ 74 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 75 struct intrhand { 76 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 77 int (*ih_func)(void *); /* handler */ 78 void *ih_arg; /* arg for handler */ 79 }; 80 #endif 81 82 static struct intrhandler { 83 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 84 TAILQ_HEAD(,intrhand) list; 85 #else 86 pxa2x0_irq_handler_t func; 87 #endif 88 void *cookie; /* NULL for stackframe */ 89 /* struct evbnt ev; */ 90 } handler[ICU_LEN]; 91 92 vaddr_t pxaic_base; 93 volatile int softint_pending; 94 volatile int intr_mask; 95 /* interrupt masks for each level */ 96 int pxa2x0_imask[NIPL]; 97 static int extirq_level[ICU_LEN]; 98 99 100 static int 101 pxaintc_match(device_t parent, cfdata_t cf, void *aux) 102 { 103 struct pxaip_attach_args *pxa = aux; 104 105 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 106 return (0); 107 108 return (1); 109 } 110 111 void 112 pxaintc_attach(device_t parent, device_t self, void *args) 113 { 114 int i; 115 116 pxaintc_attached = 1; 117 118 aprint_normal(": Interrupt Controller\n"); 119 120 #define SAIPIC_ICCR 0x14 121 122 write_icu(SAIPIC_ICCR, 1); 123 write_icu(SAIPIC_MR, 0); 124 125 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 126 handler[i].func = stray_interrupt; 127 handler[i].cookie = (void *)(intptr_t) i; 128 extirq_level[i] = IPL_SERIAL; 129 } 130 131 init_interrupt_masks(); 132 133 _splraise(IPL_SERIAL); 134 enable_interrupts(I32_bit); 135 } 136 137 /* 138 * Invoked very early on from the board-specific initarm(), in order to 139 * inform us the virtual address of the interrupt controller's registers. 140 */ 141 void 142 pxa2x0_intr_bootstrap(vaddr_t addr) 143 { 144 145 pxaic_base = addr; 146 } 147 148 /* 149 * called from irq_entry. 150 */ 151 void 152 pxa2x0_irq_handler(void *arg) 153 { 154 struct clockframe *frame = arg; 155 uint32_t irqbits; 156 int irqno; 157 int saved_spl_level; 158 159 saved_spl_level = curcpu()->ci_cpl; 160 161 /* get pending IRQs */ 162 irqbits = read_icu(SAIPIC_IP); 163 164 while ((irqno = find_first_bit(irqbits)) >= 0) { 165 /* XXX: Should we handle IRQs in priority order? */ 166 167 /* raise spl to stop interrupts of lower priorities */ 168 if (saved_spl_level < extirq_level[irqno]) 169 pxa2x0_setipl(extirq_level[irqno]); 170 171 #ifdef notyet 172 /* Enable interrupt */ 173 #endif 174 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 175 (* handler[irqno].func)( 176 handler[irqno].cookie == 0 177 ? frame : handler[irqno].cookie ); 178 #else 179 /* process all handlers for this interrupt. 180 XXX not yet */ 181 #endif 182 183 #ifdef notyet 184 /* Disable interrupt */ 185 #endif 186 187 irqbits &= ~(1<<irqno); 188 } 189 190 /* restore spl to that was when this interrupt happen */ 191 pxa2x0_setipl(saved_spl_level); 192 193 #ifdef __HAVE_FAST_SOFTINTS 194 cpu_dosoftints(); 195 #endif 196 } 197 198 static int 199 stray_interrupt(void *cookie) 200 { 201 int irqno = (int)cookie; 202 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 203 204 printf("stray interrupt %d\n", irqno); 205 206 if (irqmin <= irqno && irqno < ICU_LEN){ 207 int save = disable_interrupts(I32_bit); 208 write_icu(SAIPIC_MR, 209 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 210 restore_interrupts(save); 211 } 212 213 return 0; 214 } 215 216 217 218 /* 219 * Interrupt Mask Handling 220 */ 221 222 void 223 pxa2x0_update_intr_masks(int irqno, int level) 224 { 225 int mask = 1U<<irqno; 226 int psw = disable_interrupts(I32_bit); 227 int i; 228 229 for(i = 0; i < level; ++i) 230 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 231 232 for( ; i < NIPL-1; ++i) 233 pxa2x0_imask[i] &= ~mask; /* Disable interrupt at upper level */ 234 235 /* 236 * Enforce a hierarchy that gives "slow" device (or devices with 237 * limited input buffer space/"real-time" requirements) a better 238 * chance at not dropping data. 239 */ 240 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 241 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 242 243 write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]); 244 245 restore_interrupts(psw); 246 } 247 248 249 static void 250 init_interrupt_masks(void) 251 { 252 253 /* 254 * disable all interrupts until handlers are installed. 255 */ 256 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 257 258 } 259 260 #undef splx 261 void 262 splx(int ipl) 263 { 264 pxa2x0_splx(ipl); 265 } 266 267 #undef _splraise 268 int 269 _splraise(int ipl) 270 { 271 return pxa2x0_splraise(ipl); 272 } 273 274 #undef _spllower 275 int 276 _spllower(int ipl) 277 { 278 return pxa2x0_spllower(ipl); 279 } 280 281 void * 282 pxa2x0_intr_establish(int irqno, int level, 283 int (*func)(void *), void *cookie) 284 { 285 int psw; 286 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 287 288 if (irqno < irqmin || irqno >= ICU_LEN) 289 panic("intr_establish: bogus irq number %d", irqno); 290 291 psw = disable_interrupts(I32_bit); 292 293 handler[irqno].cookie = cookie; 294 handler[irqno].func = func; 295 extirq_level[irqno] = level; 296 pxa2x0_update_intr_masks(irqno, level); 297 298 intr_mask = pxa2x0_imask[curcpu()->ci_cpl]; 299 300 restore_interrupts(psw); 301 302 return (&handler[irqno]); 303 } 304 305 void 306 pxa2x0_intr_disestablish(void *cookie) 307 { 308 struct intrhandler *lhandler = cookie, *ih; 309 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 310 int irqno = lhandler - handler; 311 int psw; 312 313 if (irqno < irqmin || irqno >= ICU_LEN) 314 panic("intr_disestablish: bogus irq number %d", irqno); 315 316 psw = disable_interrupts(I32_bit); 317 318 ih = &handler[irqno]; 319 ih->func = stray_interrupt; 320 ih->cookie = (void *)(intptr_t)irqno; 321 extirq_level[irqno] = IPL_SERIAL; 322 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 323 324 restore_interrupts(psw); 325 } 326 327 /* 328 * Glue for drivers of sa11x0 compatible integrated logics. 329 */ 330 void * 331 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 332 int (*ih_fun)(void *), void *ih_arg) 333 { 334 335 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 336 } 337