1 /* $NetBSD: pxa2x0_intr.c,v 1.20 2012/07/29 00:07:10 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Genetec Corporation. 19 * 4. The name of Genetec Corporation may not be used to endorse or 20 * promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * IRQ handler for the Intel PXA2X0 processor. 38 * It has integrated interrupt controller. 39 */ 40 41 #include <sys/cdefs.h> 42 __KERNEL_RCSID(0, "$NetBSD: pxa2x0_intr.c,v 1.20 2012/07/29 00:07:10 matt Exp $"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/malloc.h> 47 48 #include <sys/bus.h> 49 #include <machine/intr.h> 50 #include <machine/lock.h> 51 52 #include <arm/xscale/pxa2x0cpu.h> 53 #include <arm/xscale/pxa2x0reg.h> 54 #include <arm/xscale/pxa2x0var.h> 55 #include <arm/xscale/pxa2x0_intr.h> 56 #include <arm/sa11x0/sa11x0_var.h> 57 58 /* 59 * INTC autoconf glue 60 */ 61 static int pxaintc_match(device_t, cfdata_t, void *); 62 static void pxaintc_attach(device_t, device_t, void *); 63 64 CFATTACH_DECL_NEW(pxaintc, 0, 65 pxaintc_match, pxaintc_attach, NULL, NULL); 66 67 static int pxaintc_attached; 68 69 static int stray_interrupt(void *); 70 static void init_interrupt_masks(void); 71 72 /* 73 * interrupt dispatch table. 74 */ 75 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 76 struct intrhand { 77 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */ 78 int (*ih_func)(void *); /* handler */ 79 void *ih_arg; /* arg for handler */ 80 }; 81 #endif 82 83 static struct intrhandler { 84 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ 85 TAILQ_HEAD(,intrhand) list; 86 #else 87 pxa2x0_irq_handler_t func; 88 #endif 89 void *cookie; /* NULL for stackframe */ 90 /* struct evbnt ev; */ 91 } handler[ICU_LEN]; 92 93 vaddr_t pxaic_base; 94 volatile int softint_pending; 95 volatile int intr_mask; 96 /* interrupt masks for each level */ 97 int pxa2x0_imask[NIPL]; 98 static int extirq_level[ICU_LEN]; 99 100 101 static int 102 pxaintc_match(device_t parent, cfdata_t cf, void *aux) 103 { 104 struct pxaip_attach_args *pxa = aux; 105 106 if (pxaintc_attached || pxa->pxa_addr != PXA2X0_INTCTL_BASE) 107 return (0); 108 109 return (1); 110 } 111 112 void 113 pxaintc_attach(device_t parent, device_t self, void *args) 114 { 115 int i; 116 117 pxaintc_attached = 1; 118 119 aprint_normal(": Interrupt Controller\n"); 120 121 #define SAIPIC_ICCR 0x14 122 123 write_icu(SAIPIC_ICCR, 1); 124 write_icu(SAIPIC_MR, 0); 125 126 for(i = 0; i < sizeof handler / sizeof handler[0]; ++i){ 127 handler[i].func = stray_interrupt; 128 handler[i].cookie = (void *)(intptr_t) i; 129 extirq_level[i] = IPL_SERIAL; 130 } 131 132 init_interrupt_masks(); 133 134 _splraise(IPL_SERIAL); 135 enable_interrupts(I32_bit); 136 } 137 138 /* 139 * Invoked very early on from the board-specific initarm(), in order to 140 * inform us the virtual address of the interrupt controller's registers. 141 */ 142 void 143 pxa2x0_intr_bootstrap(vaddr_t addr) 144 { 145 146 pxaic_base = addr; 147 } 148 149 static inline void 150 __raise(int ipl) 151 { 152 153 if (curcpu()->ci_cpl < ipl) 154 pxa2x0_setipl(ipl); 155 } 156 157 /* 158 * called from irq_entry. 159 */ 160 void 161 pxa2x0_irq_handler(void *arg) 162 { 163 struct clockframe *frame = arg; 164 uint32_t irqbits; 165 int irqno; 166 int saved_spl_level; 167 168 saved_spl_level = curcpu()->ci_cpl; 169 170 /* get pending IRQs */ 171 irqbits = read_icu(SAIPIC_IP); 172 173 while ((irqno = find_first_bit(irqbits)) >= 0) { 174 /* XXX: Shuould we handle IRQs in priority order? */ 175 176 /* raise spl to stop interrupts of lower priorities */ 177 if (saved_spl_level < extirq_level[irqno]) 178 pxa2x0_setipl(extirq_level[irqno]); 179 180 #ifdef notyet 181 /* Enable interrupt */ 182 #endif 183 #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ 184 (* handler[irqno].func)( 185 handler[irqno].cookie == 0 186 ? frame : handler[irqno].cookie ); 187 #else 188 /* process all handlers for this interrupt. 189 XXX not yet */ 190 #endif 191 192 #ifdef notyet 193 /* Disable interrupt */ 194 #endif 195 196 irqbits &= ~(1<<irqno); 197 } 198 199 /* restore spl to that was when this interrupt happen */ 200 pxa2x0_setipl(saved_spl_level); 201 202 #ifdef __HAVE_FAST_SOFTINTS 203 cpu_dosoftints(); 204 #endif 205 } 206 207 static int 208 stray_interrupt(void *cookie) 209 { 210 int irqno = (int)cookie; 211 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 212 213 printf("stray interrupt %d\n", irqno); 214 215 if (irqmin <= irqno && irqno < ICU_LEN){ 216 int save = disable_interrupts(I32_bit); 217 write_icu(SAIPIC_MR, 218 read_icu(SAIPIC_MR) & ~(1U<<irqno)); 219 restore_interrupts(save); 220 } 221 222 return 0; 223 } 224 225 226 227 /* 228 * Interrupt Mask Handling 229 */ 230 231 void 232 pxa2x0_update_intr_masks(int irqno, int level) 233 { 234 int mask = 1U<<irqno; 235 int psw = disable_interrupts(I32_bit); 236 int i; 237 238 for(i = 0; i < level; ++i) 239 pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ 240 241 for( ; i < NIPL-1; ++i) 242 pxa2x0_imask[i] &= ~mask; /* Disable interrupt at upper level */ 243 244 /* 245 * Enforce a hierarchy that gives "slow" device (or devices with 246 * limited input buffer space/"real-time" requirements) a better 247 * chance at not dropping data. 248 */ 249 pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM]; 250 pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED]; 251 252 write_icu(SAIPIC_MR, pxa2x0_imask[curcpu()->ci_cpl]); 253 254 restore_interrupts(psw); 255 } 256 257 258 static void 259 init_interrupt_masks(void) 260 { 261 262 /* 263 * disable all interrups until handlers are installed. 264 */ 265 memset(pxa2x0_imask, 0, sizeof(pxa2x0_imask)); 266 267 } 268 269 #undef splx 270 void 271 splx(int ipl) 272 { 273 pxa2x0_splx(ipl); 274 } 275 276 #undef _splraise 277 int 278 _splraise(int ipl) 279 { 280 return pxa2x0_splraise(ipl); 281 } 282 283 #undef _spllower 284 int 285 _spllower(int ipl) 286 { 287 return pxa2x0_spllower(ipl); 288 } 289 290 void * 291 pxa2x0_intr_establish(int irqno, int level, 292 int (*func)(void *), void *cookie) 293 { 294 int psw; 295 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 296 297 if (irqno < irqmin || irqno >= ICU_LEN) 298 panic("intr_establish: bogus irq number %d", irqno); 299 300 psw = disable_interrupts(I32_bit); 301 302 handler[irqno].cookie = cookie; 303 handler[irqno].func = func; 304 extirq_level[irqno] = level; 305 pxa2x0_update_intr_masks(irqno, level); 306 307 intr_mask = pxa2x0_imask[curcpu()->ci_cpl]; 308 309 restore_interrupts(psw); 310 311 return (&handler[irqno]); 312 } 313 314 void 315 pxa2x0_intr_disestablish(void *cookie) 316 { 317 struct intrhandler *lhandler = cookie, *ih; 318 int irqmin = CPU_IS_PXA250 ? PXA250_IRQ_MIN : PXA270_IRQ_MIN; 319 int irqno = lhandler - handler; 320 int psw; 321 322 if (irqno < irqmin || irqno >= ICU_LEN) 323 panic("intr_disestablish: bogus irq number %d", irqno); 324 325 psw = disable_interrupts(I32_bit); 326 327 ih = &handler[irqno]; 328 ih->func = stray_interrupt; 329 ih->cookie = (void *)(intptr_t)irqno; 330 extirq_level[irqno] = IPL_SERIAL; 331 pxa2x0_update_intr_masks(irqno, IPL_SERIAL); 332 333 restore_interrupts(psw); 334 } 335 336 /* 337 * Glue for drivers of sa11x0 compatible integrated logics. 338 */ 339 void * 340 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level, 341 int (*ih_fun)(void *), void *ih_arg) 342 { 343 344 return pxa2x0_intr_establish(irq, level, ih_fun, ih_arg); 345 } 346