1 /* $NetBSD: ixp425_timer.c,v 1.14 2008/01/20 16:28:24 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ixp425_timer.c,v 1.14 2008/01/20 16:28:24 joerg Exp $"); 38 39 #include "opt_ixp425.h" 40 #include "opt_perfctrs.h" 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/atomic.h> 47 #include <sys/time.h> 48 #include <sys/timetc.h> 49 #include <sys/device.h> 50 51 #include <dev/clock_subr.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 56 #include <arm/cpufunc.h> 57 58 #include <arm/xscale/ixp425reg.h> 59 #include <arm/xscale/ixp425var.h> 60 #include <arm/xscale/ixp425_sipvar.h> 61 62 static int ixpclk_match(struct device *, struct cfdata *, void *); 63 static void ixpclk_attach(struct device *, struct device *, void *); 64 static u_int ixpclk_get_timecount(struct timecounter *); 65 66 static uint32_t counts_per_hz; 67 68 static void *clock_ih; 69 70 /* callback functions for intr_functions */ 71 int ixpclk_intr(void *); 72 73 struct ixpclk_softc { 74 struct device sc_dev; 75 bus_addr_t sc_baseaddr; 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 }; 79 80 #ifndef IXP425_CLOCK_FREQ 81 #define COUNTS_PER_SEC 66666600 /* 66MHz */ 82 #else 83 #define COUNTS_PER_SEC IXP425_CLOCK_FREQ 84 #endif 85 #define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) 86 87 static struct ixpclk_softc *ixpclk_sc; 88 89 static struct timecounter ixpclk_timecounter = { 90 ixpclk_get_timecount, /* get_timecount */ 91 0, /* no poll_pps */ 92 0xffffffff, /* counter_mask */ 93 COUNTS_PER_SEC, /* frequency */ 94 "ixpclk", /* name */ 95 100, /* quality */ 96 NULL, /* prev */ 97 NULL, /* next */ 98 }; 99 100 static volatile uint32_t ixpclk_base; 101 102 CFATTACH_DECL(ixpclk, sizeof(struct ixpclk_softc), 103 ixpclk_match, ixpclk_attach, NULL, NULL); 104 105 #define GET_TIMER_VALUE(sc) (bus_space_read_4((sc)->sc_iot, \ 106 (sc)->sc_ioh, \ 107 IXP425_OST_TIM0)) 108 109 #define GET_TS_VALUE(sc) (*(volatile u_int32_t *) \ 110 (IXP425_TIMER_VBASE + IXP425_OST_TS)) 111 112 static int 113 ixpclk_match(struct device *parent, struct cfdata *match, void *aux) 114 { 115 return 2; 116 } 117 118 static void 119 ixpclk_attach(struct device *parent, struct device *self, void *aux) 120 { 121 struct ixpclk_softc *sc = (struct ixpclk_softc*) self; 122 struct ixpsip_attach_args *sa = aux; 123 124 printf("\n"); 125 126 ixpclk_sc = sc; 127 128 sc->sc_iot = sa->sa_iot; 129 sc->sc_baseaddr = sa->sa_addr; 130 131 if (bus_space_map(sc->sc_iot, sa->sa_addr, sa->sa_size, 0, 132 &sc->sc_ioh)) 133 panic("%s: Cannot map registers", self->dv_xname); 134 135 aprint_normal("%s: IXP425 Interval Timer\n", sc->sc_dev.dv_xname); 136 } 137 138 /* 139 * cpu_initclocks: 140 * 141 * Initialize the clock and get them going. 142 */ 143 void 144 cpu_initclocks(void) 145 { 146 struct ixpclk_softc* sc = ixpclk_sc; 147 u_int oldirqstate; 148 #if defined(PERFCTRS) 149 void *pmu_ih; 150 #endif 151 152 if (hz < 50 || COUNTS_PER_SEC % hz) { 153 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz); 154 hz = 100; 155 } 156 157 /* 158 * We only have one timer available; stathz and profhz are 159 * always left as 0 (the upper-layer clock code deals with 160 * this situation). 161 */ 162 if (stathz != 0) 163 aprint_error("Cannot get %d Hz statclock\n", stathz); 164 stathz = 0; 165 166 if (profhz != 0) 167 aprint_error("Cannot get %d Hz profclock\n", profhz); 168 profhz = 0; 169 170 /* Report the clock frequency. */ 171 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 172 173 oldirqstate = disable_interrupts(I32_bit); 174 175 /* Hook up the clock interrupt handler. */ 176 clock_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK, 177 ixpclk_intr, NULL); 178 if (clock_ih == NULL) 179 panic("cpu_initclocks: unable to register timer interrupt"); 180 181 #if defined(PERFCTRS) 182 pmu_ih = ixp425_intr_establish(IXP425_INT_XPMU, IPL_STATCLOCK, 183 xscale_pmc_dispatch, NULL); 184 if (pmu_ih == NULL) 185 panic("cpu_initclocks: unable to register timer interrupt"); 186 #endif 187 188 /* Set up the new clock parameters. */ 189 190 /* clear interrupt */ 191 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 192 OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT | 193 OST_TIM1_INT | OST_TIM0_INT); 194 195 counts_per_hz = COUNTS_PER_SEC / hz; 196 197 /* reload value & Timer enable */ 198 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD, 199 (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN); 200 201 restore_interrupts(oldirqstate); 202 203 tc_init(&ixpclk_timecounter); 204 } 205 206 /* 207 * setstatclockrate: 208 * 209 * Set the rate of the statistics clock. 210 * 211 * We assume that hz is either stathz or profhz, and that neither 212 * will change after being set by cpu_initclocks(). We could 213 * recalculate the intervals here, but that would be a pain. 214 */ 215 void 216 setstatclockrate(int newhz) 217 { 218 219 /* 220 * XXX Use TMR1? 221 */ 222 } 223 224 static u_int 225 ixpclk_get_timecount(struct timecounter *tc) 226 { 227 u_int savedints, base, counter; 228 229 savedints = disable_interrupts(I32_bit); 230 base = ixpclk_base; 231 counter = GET_TIMER_VALUE(ixpclk_sc); 232 restore_interrupts(savedints); 233 234 return base - counter; 235 } 236 237 /* 238 * delay: 239 * 240 * Delay for at least N microseconds. 241 */ 242 void 243 delay(u_int n) 244 { 245 u_int32_t first, last; 246 int usecs; 247 248 if (n == 0) 249 return; 250 251 /* 252 * Clamp the timeout at a maximum value (about 32 seconds with 253 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 254 * near that length of time and if they are, they should be hung 255 * out to dry. 256 */ 257 if (n >= (0x80000000U / COUNTS_PER_USEC)) 258 usecs = (0x80000000U / COUNTS_PER_USEC) - 1; 259 else 260 usecs = n * COUNTS_PER_USEC; 261 262 /* Note: Timestamp timer counts *up*, unlike the other timers */ 263 first = GET_TS_VALUE(); 264 265 while (usecs > 0) { 266 last = GET_TS_VALUE(); 267 usecs -= (int)(last - first); 268 first = last; 269 } 270 } 271 272 /* 273 * ixpclk_intr: 274 * 275 * Handle the hardclock interrupt. 276 */ 277 int 278 ixpclk_intr(void *arg) 279 { 280 struct ixpclk_softc* sc = ixpclk_sc; 281 struct clockframe *frame = arg; 282 283 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, 284 OST_TIM0_INT); 285 286 atomic_add_32(&ixpclk_base, counts_per_hz); 287 288 hardclock(frame); 289 290 return (1); 291 } 292