1 /* $NetBSD: i80321_timer.c,v 1.13 2005/12/24 20:06:52 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Timer/clock support for the Intel i80321 I/O processor. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_timer.c,v 1.13 2005/12/24 20:06:52 perry Exp $"); 44 45 #include "opt_perfctrs.h" 46 #include "opt_i80321.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/time.h> 52 53 #include <dev/clock_subr.h> 54 55 #include <machine/bus.h> 56 #include <arm/cpufunc.h> 57 58 #include <arm/xscale/i80321reg.h> 59 #include <arm/xscale/i80321var.h> 60 61 #include <arm/xscale/xscalevar.h> 62 63 void (*i80321_hardclock_hook)(void); 64 65 #ifndef COUNTS_PER_SEC 66 #define COUNTS_PER_SEC 200000000 /* 200MHz */ 67 #endif 68 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) 69 70 static void *clock_ih; 71 72 static uint32_t counts_per_hz; 73 74 int clockhandler(void *); 75 76 static inline uint32_t 77 tmr0_read(void) 78 { 79 uint32_t rv; 80 81 __asm volatile("mrc p6, 0, %0, c0, c1, 0" 82 : "=r" (rv)); 83 return (rv); 84 } 85 86 static inline void 87 tmr0_write(uint32_t val) 88 { 89 90 __asm volatile("mcr p6, 0, %0, c0, c1, 0" 91 : 92 : "r" (val)); 93 } 94 95 static inline uint32_t 96 tcr0_read(void) 97 { 98 uint32_t rv; 99 100 __asm volatile("mrc p6, 0, %0, c2, c1, 0" 101 : "=r" (rv)); 102 return (rv); 103 } 104 105 static inline void 106 tcr0_write(uint32_t val) 107 { 108 109 __asm volatile("mcr p6, 0, %0, c2, c1, 0" 110 : 111 : "r" (val)); 112 } 113 114 static inline void 115 trr0_write(uint32_t val) 116 { 117 118 __asm volatile("mcr p6, 0, %0, c4, c1, 0" 119 : 120 : "r" (val)); 121 } 122 123 static inline void 124 tisr_write(uint32_t val) 125 { 126 127 __asm volatile("mcr p6, 0, %0, c6, c1, 0" 128 : 129 : "r" (val)); 130 } 131 132 /* 133 * i80321_calibrate_delay: 134 * 135 * Calibrate the delay loop. 136 */ 137 void 138 i80321_calibrate_delay(void) 139 { 140 141 /* 142 * Just use hz=100 for now -- we'll adjust it, if necessary, 143 * in cpu_initclocks(). 144 */ 145 counts_per_hz = COUNTS_PER_SEC / 100; 146 147 tmr0_write(0); /* stop timer */ 148 tisr_write(TISR_TMR0); /* clear interrupt */ 149 trr0_write(counts_per_hz); /* reload value */ 150 tcr0_write(counts_per_hz); /* current value */ 151 152 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 153 } 154 155 /* 156 * cpu_initclocks: 157 * 158 * Initialize the clock and get them going. 159 */ 160 void 161 cpu_initclocks(void) 162 { 163 u_int oldirqstate; 164 #if defined(PERFCTRS) 165 void *pmu_ih; 166 #endif 167 168 if (hz < 50 || COUNTS_PER_SEC % hz) { 169 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz); 170 hz = 100; 171 } 172 tick = 1000000 / hz; /* number of microseconds between interrupts */ 173 tickfix = 1000000 - (hz * tick); 174 if (tickfix) { 175 int ftp; 176 177 ftp = min(ffs(tickfix), ffs(hz)); 178 tickfix >>= (ftp - 1); 179 tickfixinterval = hz >> (ftp - 1); 180 } 181 182 /* 183 * We only have one timer available; stathz and profhz are 184 * always left as 0 (the upper-layer clock code deals with 185 * this situation). 186 */ 187 if (stathz != 0) 188 aprint_error("Cannot get %d Hz statclock\n", stathz); 189 stathz = 0; 190 191 if (profhz != 0) 192 aprint_error("Cannot get %d Hz profclock\n", profhz); 193 profhz = 0; 194 195 /* Report the clock frequency. */ 196 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 197 198 oldirqstate = disable_interrupts(I32_bit); 199 200 /* Hook up the clock interrupt handler. */ 201 clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK, 202 clockhandler, NULL); 203 if (clock_ih == NULL) 204 panic("cpu_initclocks: unable to register timer interrupt"); 205 206 #if defined(PERFCTRS) 207 pmu_ih = i80321_intr_establish(ICU_INT_PMU, IPL_STATCLOCK, 208 xscale_pmc_dispatch, NULL); 209 if (pmu_ih == NULL) 210 panic("cpu_initclocks: unable to register timer interrupt"); 211 #endif 212 213 /* Set up the new clock parameters. */ 214 215 tmr0_write(0); /* stop timer */ 216 tisr_write(TISR_TMR0); /* clear interrupt */ 217 218 counts_per_hz = COUNTS_PER_SEC / hz; 219 220 trr0_write(counts_per_hz); /* reload value */ 221 tcr0_write(counts_per_hz); /* current value */ 222 223 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 224 225 restore_interrupts(oldirqstate); 226 } 227 228 /* 229 * setstatclockrate: 230 * 231 * Set the rate of the statistics clock. 232 * 233 * We assume that hz is either stathz or profhz, and that neither 234 * will change after being set by cpu_initclocks(). We could 235 * recalculate the intervals here, but that would be a pain. 236 */ 237 void 238 setstatclockrate(int newhz) 239 { 240 241 /* 242 * XXX Use TMR1? 243 */ 244 } 245 246 /* 247 * microtime: 248 * 249 * Fill in the specified timeval struct with the current time 250 * accurate to the microsecond. 251 */ 252 void 253 microtime(struct timeval *tvp) 254 { 255 static struct timeval lasttv; 256 u_int oldirqstate; 257 uint32_t counts; 258 259 oldirqstate = disable_interrupts(I32_bit); 260 261 counts = counts_per_hz - tcr0_read(); 262 263 /* Fill in the timeval struct. */ 264 *tvp = time; 265 tvp->tv_usec += (counts / COUNTS_PER_USEC); 266 267 /* Make sure microseconds doesn't overflow. */ 268 while (tvp->tv_usec >= 1000000) { 269 tvp->tv_usec -= 1000000; 270 tvp->tv_sec++; 271 } 272 273 /* Make sure the time has advanced. */ 274 if (tvp->tv_sec == lasttv.tv_sec && 275 tvp->tv_usec <= lasttv.tv_usec) { 276 tvp->tv_usec = lasttv.tv_usec + 1; 277 if (tvp->tv_usec >= 1000000) { 278 tvp->tv_usec -= 1000000; 279 tvp->tv_sec++; 280 } 281 } 282 283 lasttv = *tvp; 284 285 restore_interrupts(oldirqstate); 286 } 287 288 /* 289 * delay: 290 * 291 * Delay for at least N microseconds. 292 */ 293 void 294 delay(u_int n) 295 { 296 uint32_t cur, last, delta, usecs; 297 298 /* 299 * This works by polling the timer and counting the 300 * number of microseconds that go by. 301 */ 302 last = tcr0_read(); 303 delta = usecs = 0; 304 305 while (n > usecs) { 306 cur = tcr0_read(); 307 308 /* Check to see if the timer has wrapped around. */ 309 if (last < cur) 310 delta += (last + (counts_per_hz - cur)); 311 else 312 delta += (last - cur); 313 314 last = cur; 315 316 if (delta >= COUNTS_PER_USEC) { 317 usecs += delta / COUNTS_PER_USEC; 318 delta %= COUNTS_PER_USEC; 319 } 320 } 321 } 322 323 todr_chip_handle_t todr_handle; 324 325 /* 326 * todr_attach: 327 * 328 * Set the specified time-of-day register as the system real-time clock. 329 */ 330 void 331 todr_attach(todr_chip_handle_t todr) 332 { 333 334 if (todr_handle) 335 panic("todr_attach: rtc already configured"); 336 todr_handle = todr; 337 } 338 339 /* 340 * inittodr: 341 * 342 * Initialize time from the time-of-day register. 343 */ 344 #define MINYEAR 2003 /* minimum plausible year */ 345 void 346 inittodr(time_t base) 347 { 348 time_t deltat; 349 int badbase; 350 351 if (base < (MINYEAR - 1970) * SECYR) { 352 printf("WARNING: preposterous time in file system"); 353 /* read the system clock anyway */ 354 base = (MINYEAR - 1970) * SECYR; 355 badbase = 1; 356 } else 357 badbase = 0; 358 359 if (todr_handle == NULL || 360 todr_gettime(todr_handle, &time) != 0 || 361 time.tv_sec == 0) { 362 /* 363 * Believe the time in the file system for lack of 364 * anything better, resetting the TODR. 365 */ 366 time.tv_sec = base; 367 time.tv_usec = 0; 368 if (todr_handle != NULL && !badbase) { 369 printf("WARNING: preposterous clock chip time\n"); 370 resettodr(); 371 } 372 goto bad; 373 } 374 375 if (!badbase) { 376 /* 377 * See if we gained/lost two or more days; if 378 * so, assume something is amiss. 379 */ 380 deltat = time.tv_sec - base; 381 if (deltat < 0) 382 deltat = -deltat; 383 if (deltat < 2 * SECDAY) 384 return; /* all is well */ 385 printf("WARNING: clock %s %ld days\n", 386 time.tv_sec < base ? "lost" : "gained", 387 (long)deltat / SECDAY); 388 } 389 bad: 390 printf("WARNING: CHECK AND RESET THE DATE!\n"); 391 } 392 393 /* 394 * resettodr: 395 * 396 * Reset the time-of-day register with the current time. 397 */ 398 void 399 resettodr(void) 400 { 401 402 if (time.tv_sec == 0) 403 return; 404 405 if (todr_handle != NULL && 406 todr_settime(todr_handle, &time) != 0) 407 printf("resettodr: failed to set time\n"); 408 } 409 410 /* 411 * clockhandler: 412 * 413 * Handle the hardclock interrupt. 414 */ 415 int 416 clockhandler(void *arg) 417 { 418 struct clockframe *frame = arg; 419 420 tisr_write(TISR_TMR0); 421 422 hardclock(frame); 423 424 if (i80321_hardclock_hook != NULL) 425 (*i80321_hardclock_hook)(); 426 427 return (1); 428 } 429