1 /* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Timer/clock support for the Intel i80321 I/O processor. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $"); 44 45 #include "opt_perfctrs.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/time.h> 51 52 #include <dev/clock_subr.h> 53 54 #include <machine/bus.h> 55 #include <arm/cpufunc.h> 56 57 #include <arm/xscale/i80321reg.h> 58 #include <arm/xscale/i80321var.h> 59 60 #include <arm/xscale/xscalevar.h> 61 62 void (*i80321_hardclock_hook)(void); 63 64 #define COUNTS_PER_SEC 200000000 /* 200MHz */ 65 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) 66 67 static void *clock_ih; 68 69 static uint32_t counts_per_hz; 70 71 int clockhandler(void *); 72 73 static __inline uint32_t 74 tmr0_read(void) 75 { 76 uint32_t rv; 77 78 __asm __volatile("mrc p6, 0, %0, c0, c1, 0" 79 : "=r" (rv)); 80 return (rv); 81 } 82 83 static __inline void 84 tmr0_write(uint32_t val) 85 { 86 87 __asm __volatile("mcr p6, 0, %0, c0, c1, 0" 88 : 89 : "r" (val)); 90 } 91 92 static __inline uint32_t 93 tcr0_read(void) 94 { 95 uint32_t rv; 96 97 __asm __volatile("mrc p6, 0, %0, c2, c1, 0" 98 : "=r" (rv)); 99 return (rv); 100 } 101 102 static __inline void 103 tcr0_write(uint32_t val) 104 { 105 106 __asm __volatile("mcr p6, 0, %0, c2, c1, 0" 107 : 108 : "r" (val)); 109 } 110 111 static __inline void 112 trr0_write(uint32_t val) 113 { 114 115 __asm __volatile("mcr p6, 0, %0, c4, c1, 0" 116 : 117 : "r" (val)); 118 } 119 120 static __inline void 121 tisr_write(uint32_t val) 122 { 123 124 __asm __volatile("mcr p6, 0, %0, c6, c1, 0" 125 : 126 : "r" (val)); 127 } 128 129 /* 130 * i80321_calibrate_delay: 131 * 132 * Calibrate the delay loop. 133 */ 134 void 135 i80321_calibrate_delay(void) 136 { 137 138 /* 139 * Just use hz=100 for now -- we'll adjust it, if necessary, 140 * in cpu_initclocks(). 141 */ 142 counts_per_hz = COUNTS_PER_SEC / 100; 143 144 tmr0_write(0); /* stop timer */ 145 tisr_write(TISR_TMR0); /* clear interrupt */ 146 trr0_write(counts_per_hz); /* reload value */ 147 tcr0_write(counts_per_hz); /* current value */ 148 149 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 150 } 151 152 /* 153 * cpu_initclocks: 154 * 155 * Initialize the clock and get them going. 156 */ 157 void 158 cpu_initclocks(void) 159 { 160 u_int oldirqstate; 161 #if defined(PERFCTRS) 162 void *pmu_ih; 163 #endif 164 165 if (hz < 50 || COUNTS_PER_SEC % hz) { 166 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz); 167 hz = 100; 168 } 169 tick = 1000000 / hz; /* number of microseconds between interrupts */ 170 tickfix = 1000000 - (hz * tick); 171 if (tickfix) { 172 int ftp; 173 174 ftp = min(ffs(tickfix), ffs(hz)); 175 tickfix >>= (ftp - 1); 176 tickfixinterval = hz >> (ftp - 1); 177 } 178 179 /* 180 * We only have one timer available; stathz and profhz are 181 * always left as 0 (the upper-layer clock code deals with 182 * this situation). 183 */ 184 if (stathz != 0) 185 aprint_error("Cannot get %d Hz statclock\n", stathz); 186 stathz = 0; 187 188 if (profhz != 0) 189 aprint_error("Cannot get %d Hz profclock\n", profhz); 190 profhz = 0; 191 192 /* Report the clock frequency. */ 193 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz); 194 195 oldirqstate = disable_interrupts(I32_bit); 196 197 /* Hook up the clock interrupt handler. */ 198 clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK, 199 clockhandler, NULL); 200 if (clock_ih == NULL) 201 panic("cpu_initclocks: unable to register timer interrupt"); 202 203 #if defined(PERFCTRS) 204 pmu_ih = i80321_intr_establish(ICU_INT_PMU, IPL_STATCLOCK, 205 xscale_pmc_dispatch, NULL); 206 if (pmu_ih == NULL) 207 panic("cpu_initclocks: unable to register timer interrupt"); 208 #endif 209 210 /* Set up the new clock parameters. */ 211 212 tmr0_write(0); /* stop timer */ 213 tisr_write(TISR_TMR0); /* clear interrupt */ 214 215 counts_per_hz = COUNTS_PER_SEC / hz; 216 217 trr0_write(counts_per_hz); /* reload value */ 218 tcr0_write(counts_per_hz); /* current value */ 219 220 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); 221 222 restore_interrupts(oldirqstate); 223 } 224 225 /* 226 * setstatclockrate: 227 * 228 * Set the rate of the statistics clock. 229 * 230 * We assume that hz is either stathz or profhz, and that neither 231 * will change after being set by cpu_initclocks(). We could 232 * recalculate the intervals here, but that would be a pain. 233 */ 234 void 235 setstatclockrate(int hz) 236 { 237 238 /* 239 * XXX Use TMR1? 240 */ 241 } 242 243 /* 244 * microtime: 245 * 246 * Fill in the specified timeval struct with the current time 247 * accurate to the microsecond. 248 */ 249 void 250 microtime(struct timeval *tvp) 251 { 252 static struct timeval lasttv; 253 u_int oldirqstate; 254 uint32_t counts; 255 256 oldirqstate = disable_interrupts(I32_bit); 257 258 counts = counts_per_hz - tcr0_read(); 259 260 /* Fill in the timeval struct. */ 261 *tvp = time; 262 tvp->tv_usec += (counts / COUNTS_PER_USEC); 263 264 /* Make sure microseconds doesn't overflow. */ 265 while (tvp->tv_usec >= 1000000) { 266 tvp->tv_usec -= 1000000; 267 tvp->tv_sec++; 268 } 269 270 /* Make sure the time has advanced. */ 271 if (tvp->tv_sec == lasttv.tv_sec && 272 tvp->tv_usec <= lasttv.tv_usec) { 273 tvp->tv_usec = lasttv.tv_usec + 1; 274 if (tvp->tv_usec >= 1000000) { 275 tvp->tv_usec -= 1000000; 276 tvp->tv_sec++; 277 } 278 } 279 280 lasttv = *tvp; 281 282 restore_interrupts(oldirqstate); 283 } 284 285 /* 286 * delay: 287 * 288 * Delay for at least N microseconds. 289 */ 290 void 291 delay(u_int n) 292 { 293 uint32_t cur, last, delta, usecs; 294 295 /* 296 * This works by polling the timer and counting the 297 * number of microseconds that go by. 298 */ 299 last = tcr0_read(); 300 delta = usecs = 0; 301 302 while (n > usecs) { 303 cur = tcr0_read(); 304 305 /* Check to see if the timer has wrapped around. */ 306 if (last < cur) 307 delta += (last + (counts_per_hz - cur)); 308 else 309 delta += (last - cur); 310 311 last = cur; 312 313 if (delta >= COUNTS_PER_USEC) { 314 usecs += delta / COUNTS_PER_USEC; 315 delta %= COUNTS_PER_USEC; 316 } 317 } 318 } 319 320 todr_chip_handle_t todr_handle; 321 322 /* 323 * todr_attach: 324 * 325 * Set the specified time-of-day register as the system real-time clock. 326 */ 327 void 328 todr_attach(todr_chip_handle_t todr) 329 { 330 331 if (todr_handle) 332 panic("todr_attach: rtc already configured"); 333 todr_handle = todr; 334 } 335 336 /* 337 * inittodr: 338 * 339 * Initialize time from the time-of-day register. 340 */ 341 #define MINYEAR 2003 /* minimum plausible year */ 342 void 343 inittodr(time_t base) 344 { 345 time_t deltat; 346 int badbase; 347 348 if (base < (MINYEAR - 1970) * SECYR) { 349 printf("WARNING: preposterous time in file system"); 350 /* read the system clock anyway */ 351 base = (MINYEAR - 1970) * SECYR; 352 badbase = 1; 353 } else 354 badbase = 0; 355 356 if (todr_handle == NULL || 357 todr_gettime(todr_handle, (struct timeval *)&time) != 0 || 358 time.tv_sec == 0) { 359 /* 360 * Believe the time in the file system for lack of 361 * anything better, resetting the TODR. 362 */ 363 time.tv_sec = base; 364 time.tv_usec = 0; 365 if (todr_handle != NULL && !badbase) { 366 printf("WARNING: preposterous clock chip time\n"); 367 resettodr(); 368 } 369 goto bad; 370 } 371 372 if (!badbase) { 373 /* 374 * See if we tained/lost two or more days; if 375 * so, assume something is amiss. 376 */ 377 deltat = time.tv_sec - base; 378 if (deltat < 0) 379 deltat = -deltat; 380 if (deltat < 2 * SECDAY) 381 return; /* all is well */ 382 printf("WARNING: clock %s %ld days\n", 383 time.tv_sec < base ? "lost" : "gained", 384 (long)deltat / SECDAY); 385 } 386 bad: 387 printf("WARNING: CHECK AND RESET THE DATE!\n"); 388 } 389 390 /* 391 * resettodr: 392 * 393 * Reset the time-of-day register with the current time. 394 */ 395 void 396 resettodr(void) 397 { 398 399 if (time.tv_sec == 0) 400 return; 401 402 if (todr_handle != NULL && 403 todr_settime(todr_handle, (struct timeval *)&time) != 0) 404 printf("resettodr: failed to set time\n"); 405 } 406 407 /* 408 * clockhandler: 409 * 410 * Handle the hardclock interrupt. 411 */ 412 int 413 clockhandler(void *arg) 414 { 415 struct clockframe *frame = arg; 416 417 tisr_write(TISR_TMR0); 418 419 hardclock(frame); 420 421 if (i80321_hardclock_hook != NULL) 422 (*i80321_hardclock_hook)(); 423 424 return (1); 425 } 426