1 /* $NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80321 I/O Processor chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/extent.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 55 #include <arm/xscale/i80321reg.h> 56 #include <arm/xscale/i80321var.h> 57 58 #include <dev/pci/ppbreg.h> 59 #include <dev/pci/pciconf.h> 60 61 #include "opt_pci.h" 62 #include "pci.h" 63 64 void i80321_pci_attach_hook(struct device *, struct device *, 65 struct pcibus_attach_args *); 66 int i80321_pci_bus_maxdevs(void *, int); 67 pcitag_t i80321_pci_make_tag(void *, int, int, int); 68 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *, 69 int *); 70 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); 71 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); 72 73 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 74 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 75 76 void 77 i80321_pci_init(pci_chipset_tag_t pc, void *cookie) 78 { 79 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 80 struct i80321_softc *sc = cookie; 81 struct extent *ioext, *memext; 82 uint32_t busno; 83 #endif 84 85 pc->pc_conf_v = cookie; 86 pc->pc_attach_hook = i80321_pci_attach_hook; 87 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs; 88 pc->pc_make_tag = i80321_pci_make_tag; 89 pc->pc_decompose_tag = i80321_pci_decompose_tag; 90 pc->pc_conf_read = i80321_pci_conf_read; 91 pc->pc_conf_write = i80321_pci_conf_write; 92 93 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 94 /* 95 * Configure the PCI bus. 96 * 97 * XXX We need to revisit this. We only configure the Secondary 98 * bus (and its children). The bus configure code needs changes 99 * to support how the busses are arranged on this chip. We also 100 * need to only configure devices in the private device space on 101 * the Secondary bus. 102 */ 103 104 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 105 busno = PCIXSR_BUSNO(busno); 106 if (busno == 0xff) 107 busno = 0; 108 109 ioext = extent_create("pciio", sc->sc_ioout_xlate, 110 sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1, 111 M_DEVBUF, NULL, 0, EX_NOWAIT); 112 memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo, 113 sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1, 114 M_DEVBUF, NULL, 0, EX_NOWAIT); 115 116 aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname); 117 pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align); 118 119 extent_destroy(ioext); 120 extent_destroy(memext); 121 #endif 122 } 123 124 void 125 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p) 126 { 127 } 128 129 void 130 i80321_pci_attach_hook(struct device *parent, struct device *self, 131 struct pcibus_attach_args *pba) 132 { 133 134 /* Nothing to do. */ 135 } 136 137 int 138 i80321_pci_bus_maxdevs(void *v, int busno) 139 { 140 141 return (32); 142 } 143 144 pcitag_t 145 i80321_pci_make_tag(void *v, int b, int d, int f) 146 { 147 148 return ((b << 16) | (d << 11) | (f << 8)); 149 } 150 151 void 152 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 153 { 154 155 if (bp != NULL) 156 *bp = (tag >> 16) & 0xff; 157 if (dp != NULL) 158 *dp = (tag >> 11) & 0x1f; 159 if (fp != NULL) 160 *fp = (tag >> 8) & 0x7; 161 } 162 163 struct pciconf_state { 164 uint32_t ps_addr_val; 165 166 int ps_b, ps_d, ps_f; 167 }; 168 169 static int 170 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset, 171 struct pciconf_state *ps) 172 { 173 uint32_t busno; 174 175 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 176 177 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 178 busno = PCIXSR_BUSNO(busno); 179 if (busno == 0xff) 180 busno = 0; 181 182 /* 183 * If the bus # is the same as our own, then use Type 0 cycles, 184 * else use Type 1. 185 * 186 * XXX We should filter out all non-private devices here! 187 * XXX How does private space interact with PCI-PCI bridges? 188 */ 189 if (ps->ps_b == busno) { 190 if (ps->ps_d > (31 - 16)) 191 return (1); 192 /* 193 * NOTE: PCI-X requires that that devices updated their 194 * PCIXSR on every config write with the device number 195 * specified in AD[15:11]. If we don't set this field, 196 * each device could end of thinking it is at device 0, 197 * which can cause a number of problems. Doing this 198 * unconditionally should be OK when only PCI devices 199 * are present. 200 */ 201 ps->ps_addr_val = (1U << (ps->ps_d + 16)) | 202 (ps->ps_d << 11) | (ps->ps_f << 8) | offset; 203 } else { 204 /* The tag is already in the correct format. */ 205 ps->ps_addr_val = tag | offset | 1; 206 } 207 208 return (0); 209 } 210 211 pcireg_t 212 i80321_pci_conf_read(void *v, pcitag_t tag, int offset) 213 { 214 struct i80321_softc *sc = v; 215 struct pciconf_state ps; 216 vaddr_t va; 217 uint32_t isr; 218 pcireg_t rv; 219 u_int s; 220 221 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 222 return ((pcireg_t) -1); 223 224 PCI_CONF_LOCK(s); 225 226 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 227 ps.ps_addr_val); 228 229 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 230 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) { 231 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR); 232 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR, 233 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM| 234 ATUISR_PTAT|ATUISR_PMPE)); 235 #if 0 236 printf("conf_read: %d/%d/%d bad address\n", 237 ps.ps_b, ps.ps_d, ps.ps_f); 238 #endif 239 rv = (pcireg_t) -1; 240 } 241 242 PCI_CONF_UNLOCK(s); 243 244 return (rv); 245 } 246 247 void 248 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 249 { 250 struct i80321_softc *sc = v; 251 struct pciconf_state ps; 252 u_int s; 253 254 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 255 return; 256 257 PCI_CONF_LOCK(s); 258 259 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 260 ps.ps_addr_val); 261 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val); 262 263 PCI_CONF_UNLOCK(s); 264 } 265