1 /* $NetBSD: i80321_pci.c,v 1.18 2020/07/07 03:38:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80321 I/O Processor chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.18 2020/07/07 03:38:46 thorpej Exp $"); 44 45 #include "opt_pci.h" 46 #include "opt_i80321.h" 47 #include "pci.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/bus.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pciconf.h> 59 #include <dev/pci/ppbreg.h> 60 61 #include <arm/locore.h> 62 63 #include <arm/xscale/i80321reg.h> 64 #include <arm/xscale/i80321var.h> 65 66 void i80321_pci_attach_hook(device_t, device_t, 67 struct pcibus_attach_args *); 68 int i80321_pci_bus_maxdevs(void *, int); 69 pcitag_t i80321_pci_make_tag(void *, int, int, int); 70 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *, 71 int *); 72 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); 73 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); 74 void i80321_pci_conf_interrupt(void *, int, int, int, int, int *); 75 76 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 77 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 78 79 void 80 i80321_pci_init(pci_chipset_tag_t pc, void *cookie) 81 { 82 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 83 struct i80321_softc *sc = cookie; 84 struct pciconf_resources *pcires; 85 uint32_t busno; 86 #endif 87 88 pc->pc_conf_v = cookie; 89 pc->pc_attach_hook = i80321_pci_attach_hook; 90 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs; 91 pc->pc_make_tag = i80321_pci_make_tag; 92 pc->pc_decompose_tag = i80321_pci_decompose_tag; 93 pc->pc_conf_read = i80321_pci_conf_read; 94 pc->pc_conf_write = i80321_pci_conf_write; 95 pc->pc_conf_interrupt = i80321_pci_conf_interrupt; 96 97 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 98 /* 99 * Configure the PCI bus. 100 * 101 * XXX We need to revisit this. We only configure the Secondary 102 * bus (and its children). The bus configure code needs changes 103 * to support how the busses are arranged on this chip. We also 104 * need to only configure devices in the private device space on 105 * the Secondary bus. 106 */ 107 108 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 109 busno = PCIXSR_BUSNO(busno); 110 if (busno == 0xff) 111 busno = 0; 112 113 pcires = pciconf_resource_init(); 114 115 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 116 sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset, 117 VERDE_OUT_XLATE_IO_WIN_SIZE - sc->sc_ioout_xlate_offset); 118 119 #ifdef I80321_USE_DIRECT_WIN 120 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 121 VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP, 122 VERDE_OUT_DIRECT_WIN_SIZE - VERDE_OUT_DIRECT_WIN_SKIP); 123 #else 124 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 125 sc->sc_owin[0].owin_xlate_lo, VERDE_OUT_XLATE_MEM_WIN_SIZE); 126 #endif 127 128 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n"); 129 pci_configure_bus(pc, pcires, busno, arm_dcache_align); 130 131 pciconf_resource_fini(pcires); 132 #endif 133 } 134 135 void 136 i80321_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 137 { 138 } 139 140 void 141 i80321_pci_attach_hook(device_t parent, device_t self, 142 struct pcibus_attach_args *pba) 143 { 144 145 /* Nothing to do. */ 146 } 147 148 int 149 i80321_pci_bus_maxdevs(void *v, int busno) 150 { 151 152 return (32); 153 } 154 155 pcitag_t 156 i80321_pci_make_tag(void *v, int b, int d, int f) 157 { 158 159 return ((b << 16) | (d << 11) | (f << 8)); 160 } 161 162 void 163 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 164 { 165 166 if (bp != NULL) 167 *bp = (tag >> 16) & 0xff; 168 if (dp != NULL) 169 *dp = (tag >> 11) & 0x1f; 170 if (fp != NULL) 171 *fp = (tag >> 8) & 0x7; 172 } 173 174 struct pciconf_state { 175 uint32_t ps_addr_val; 176 177 int ps_b, ps_d, ps_f; 178 }; 179 180 static int 181 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset, 182 struct pciconf_state *ps) 183 { 184 uint32_t busno; 185 186 if ((unsigned int)offset >= PCI_CONF_SIZE) 187 return (1); 188 189 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 190 191 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 192 busno = PCIXSR_BUSNO(busno); 193 if (busno == 0xff) 194 busno = 0; 195 196 /* 197 * If the bus # is the same as our own, then use Type 0 cycles, 198 * else use Type 1. 199 * 200 * XXX We should filter out all non-private devices here! 201 * XXX How does private space interact with PCI-PCI bridges? 202 */ 203 if (ps->ps_b == busno) { 204 if (ps->ps_d > (31 - 16)) 205 return (1); 206 /* 207 * NOTE: PCI-X requires that that devices updated their 208 * PCIXSR on every config write with the device number 209 * specified in AD[15:11]. If we don't set this field, 210 * each device could end of thinking it is at device 0, 211 * which can cause a number of problems. Doing this 212 * unconditionally should be OK when only PCI devices 213 * are present. 214 */ 215 ps->ps_addr_val = (1U << (ps->ps_d + 16)) | 216 (ps->ps_d << 11) | (ps->ps_f << 8) | offset; 217 } else { 218 /* The tag is already in the correct format. */ 219 ps->ps_addr_val = tag | offset | 1; 220 } 221 222 return (0); 223 } 224 225 pcireg_t 226 i80321_pci_conf_read(void *v, pcitag_t tag, int offset) 227 { 228 struct i80321_softc *sc = v; 229 struct pciconf_state ps; 230 vaddr_t va; 231 uint32_t isr; 232 pcireg_t rv; 233 u_int s; 234 235 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 236 return ((pcireg_t) -1); 237 238 PCI_CONF_LOCK(s); 239 240 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 241 ps.ps_addr_val); 242 243 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 244 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) { 245 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR); 246 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR, 247 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM| 248 ATUISR_PTAT|ATUISR_PMPE)); 249 #if 0 250 printf("conf_read: %d/%d/%d bad address\n", 251 ps.ps_b, ps.ps_d, ps.ps_f); 252 #endif 253 rv = (pcireg_t) -1; 254 } 255 256 PCI_CONF_UNLOCK(s); 257 258 return (rv); 259 } 260 261 void 262 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 263 { 264 struct i80321_softc *sc = v; 265 struct pciconf_state ps; 266 u_int s; 267 268 if (i80321_pci_conf_setup(sc, tag, offset, &ps)) 269 return; 270 271 PCI_CONF_LOCK(s); 272 273 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR, 274 ps.ps_addr_val); 275 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val); 276 277 PCI_CONF_UNLOCK(s); 278 } 279