xref: /netbsd-src/sys/arch/arm/xscale/i80321_mcu.c (revision ed9977b1224ae46b1df090a9d378605dde53e47b)
1*ed9977b1Sdyoung /*	$NetBSD: i80321_mcu.c,v 1.4 2011/07/01 20:32:51 dyoung Exp $	*/
2f5362116Sthorpej 
3f5362116Sthorpej /*
4f5362116Sthorpej  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5f5362116Sthorpej  * All rights reserved.
6f5362116Sthorpej  *
7f5362116Sthorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8f5362116Sthorpej  *
9f5362116Sthorpej  * Redistribution and use in source and binary forms, with or without
10f5362116Sthorpej  * modification, are permitted provided that the following conditions
11f5362116Sthorpej  * are met:
12f5362116Sthorpej  * 1. Redistributions of source code must retain the above copyright
13f5362116Sthorpej  *    notice, this list of conditions and the following disclaimer.
14f5362116Sthorpej  * 2. Redistributions in binary form must reproduce the above copyright
15f5362116Sthorpej  *    notice, this list of conditions and the following disclaimer in the
16f5362116Sthorpej  *    documentation and/or other materials provided with the distribution.
17f5362116Sthorpej  * 3. All advertising materials mentioning features or use of this software
18f5362116Sthorpej  *    must display the following acknowledgement:
19f5362116Sthorpej  *	This product includes software developed for the NetBSD Project by
20f5362116Sthorpej  *	Wasabi Systems, Inc.
21f5362116Sthorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22f5362116Sthorpej  *    or promote products derived from this software without specific prior
23f5362116Sthorpej  *    written permission.
24f5362116Sthorpej  *
25f5362116Sthorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26f5362116Sthorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27f5362116Sthorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28f5362116Sthorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29f5362116Sthorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30f5362116Sthorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31f5362116Sthorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32f5362116Sthorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33f5362116Sthorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34f5362116Sthorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35f5362116Sthorpej  * POSSIBILITY OF SUCH DAMAGE.
36f5362116Sthorpej  */
37f5362116Sthorpej 
38f5362116Sthorpej /*
39f5362116Sthorpej  * Intel i80321 I/O Processor memory controller support.
40f5362116Sthorpej  */
41f5362116Sthorpej 
4208716eaeSlukem #include <sys/cdefs.h>
43*ed9977b1Sdyoung __KERNEL_RCSID(0, "$NetBSD: i80321_mcu.c,v 1.4 2011/07/01 20:32:51 dyoung Exp $");
4408716eaeSlukem 
45f5362116Sthorpej #include <sys/param.h>
46f5362116Sthorpej #include <sys/systm.h>
47f5362116Sthorpej 
48*ed9977b1Sdyoung #include <sys/bus.h>
49f5362116Sthorpej 
50f5362116Sthorpej #include <arm/xscale/i80321reg.h>
51f5362116Sthorpej #include <arm/xscale/i80321var.h>
52f5362116Sthorpej 
53f5362116Sthorpej /*
54f5362116Sthorpej  * i80321_sdram_bounds:
55f5362116Sthorpej  *
56f5362116Sthorpej  *	Retrieve the start and size of SDRAM.
57f5362116Sthorpej  */
58f5362116Sthorpej void
i80321_sdram_bounds(bus_space_tag_t st,bus_space_handle_t sh,paddr_t * start,psize_t * size)59f5362116Sthorpej i80321_sdram_bounds(bus_space_tag_t st, bus_space_handle_t sh,
60f5362116Sthorpej     paddr_t *start, psize_t *size)
61f5362116Sthorpej {
62f5362116Sthorpej 	uint32_t sdbr, sbr0, sbr1;
63f5362116Sthorpej 	uint32_t bank0, bank1;
64f5362116Sthorpej 
65f5362116Sthorpej 	sdbr = bus_space_read_4(st, sh, MCU_SDBR);
66f5362116Sthorpej 	sbr0 = bus_space_read_4(st, sh, MCU_SBR0);
67f5362116Sthorpej 	sbr1 = bus_space_read_4(st, sh, MCU_SBR1);
68f5362116Sthorpej 
69f5362116Sthorpej #ifdef VERBOSE_INIT_ARM
70f5362116Sthorpej 	printf("i80321: SBDR = 0x%08x SBR0 = 0x%08x SBR1 = 0x%08x\n",
71f5362116Sthorpej 	    sdbr, sbr0, sbr1);
72f5362116Sthorpej #endif
73f5362116Sthorpej 
74f5362116Sthorpej 	*start = sdbr;
75f5362116Sthorpej 
76f5362116Sthorpej 	sdbr = (sdbr >> 25) & 0x1f;
77f5362116Sthorpej 
78f5362116Sthorpej 	sbr0 &= 0x3f;
79f5362116Sthorpej 	sbr1 &= 0x3f;
80f5362116Sthorpej 
81f5362116Sthorpej 	bank0 = (sbr0 - sdbr) << 25;
82f5362116Sthorpej 	bank1 = (sbr1 - sbr0) << 25;
83f5362116Sthorpej 
84f5362116Sthorpej #ifdef VERBOSE_INIT_ARM
85f5362116Sthorpej 	printf("i80321: BANK0 = 0x%08x BANK1 = 0x%08x\n", bank0, bank1);
86f5362116Sthorpej #endif
87f5362116Sthorpej 
88f5362116Sthorpej 	*size = bank0 + bank1;
89f5362116Sthorpej }
90