1 /* $NetBSD: i80312_pci.c,v 1.15 2014/01/28 12:02:48 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.15 2014/01/28 12:02:48 martin Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/extent.h> 52 #include <sys/malloc.h> 53 #include <sys/bus.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pciconf.h> 59 #include <dev/pci/ppbreg.h> 60 61 #include <arm/locore.h> 62 63 #include <arm/xscale/i80312reg.h> 64 #include <arm/xscale/i80312var.h> 65 66 void i80312_pci_attach_hook(device_t, device_t, 67 struct pcibus_attach_args *); 68 int i80312_pci_bus_maxdevs(void *, int); 69 pcitag_t i80312_pci_make_tag(void *, int, int, int); 70 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *, 71 int *); 72 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int); 73 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t); 74 void i80312_pci_conf_interrupt(void *, int, int, int, int, int *); 75 76 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 77 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 78 79 void 80 i80312_pci_init(pci_chipset_tag_t pc, void *cookie) 81 { 82 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 83 struct i80312_softc *sc = cookie; 84 struct extent *ioext, *memext; 85 pcireg_t binfo; 86 int sbus; 87 #endif 88 89 pc->pc_conf_v = cookie; 90 pc->pc_attach_hook = i80312_pci_attach_hook; 91 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs; 92 pc->pc_make_tag = i80312_pci_make_tag; 93 pc->pc_decompose_tag = i80312_pci_decompose_tag; 94 pc->pc_conf_read = i80312_pci_conf_read; 95 pc->pc_conf_write = i80312_pci_conf_write; 96 pc->pc_conf_interrupt = i80312_pci_conf_interrupt; 97 98 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 99 /* 100 * Configure the PCI bus. 101 * 102 * XXX We need to revisit this. We only configure the Secondary 103 * bus (and its children). The bus configure code needs changes 104 * to support how the busses are arranged on this chip. We also 105 * need to only configure devices in the private device space on 106 * the Secondary bus. 107 */ 108 109 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 110 /* pbus = PPB_BUSINFO_PRIMARY(binfo); */ 111 sbus = PPB_BUSINFO_SECONDARY(binfo); 112 113 ioext = extent_create("pciio", sc->sc_sioout_base, 114 sc->sc_sioout_base + sc->sc_sioout_size - 1, 115 NULL, 0, EX_NOWAIT); 116 memext = extent_create("pcimem", sc->sc_smemout_base, 117 sc->sc_smemout_base + sc->sc_smemout_size - 1, 118 NULL, 0, EX_NOWAIT); 119 120 aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n"); 121 pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align); 122 123 extent_destroy(ioext); 124 extent_destroy(memext); 125 #endif 126 } 127 128 void 129 i80312_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 130 { 131 } 132 133 void 134 i80312_pci_attach_hook(device_t parent, device_t self, 135 struct pcibus_attach_args *pba) 136 { 137 138 /* Nothing to do. */ 139 } 140 141 int 142 i80312_pci_bus_maxdevs(void *v, int busno) 143 { 144 145 return (32); 146 } 147 148 pcitag_t 149 i80312_pci_make_tag(void *v, int b, int d, int f) 150 { 151 152 return ((b << 16) | (d << 11) | (f << 8)); 153 } 154 155 void 156 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 157 { 158 159 if (bp != NULL) 160 *bp = (tag >> 16) & 0xff; 161 if (dp != NULL) 162 *dp = (tag >> 11) & 0x1f; 163 if (fp != NULL) 164 *fp = (tag >> 8) & 0x7; 165 } 166 167 struct pciconf_state { 168 bus_addr_t ps_addr_reg; 169 bus_addr_t ps_data_reg; 170 bus_addr_t ps_csr_reg; 171 uint32_t ps_addr_val; 172 173 int ps_b, ps_d, ps_f; 174 }; 175 176 static int 177 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset, 178 struct pciconf_state *ps) 179 { 180 pcireg_t binfo; 181 int pbus, sbus; 182 183 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 184 185 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 186 pbus = PPB_BUSINFO_PRIMARY(binfo); 187 sbus = PPB_BUSINFO_SECONDARY(binfo); 188 189 /* 190 * If the bus # is the Primary bus #, use the Primary 191 * Address/Data registers, otherwise use the Secondary 192 * Address/Data registers. 193 */ 194 if (ps->ps_b == pbus) { 195 ps->ps_addr_reg = I80312_ATU_POCCA; 196 ps->ps_data_reg = I80312_ATU_POCCD; 197 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG; 198 } else { 199 ps->ps_addr_reg = I80312_ATU_SOCCA; 200 ps->ps_data_reg = I80312_ATU_SOCCD; 201 ps->ps_csr_reg = I80312_ATU_SACS; 202 } 203 204 /* 205 * If the bus # is the Primary or Secondary bus #, then use 206 * Type 0 cycles, else use Type 1. 207 * 208 * XXX We should filter out all non-private devices here! 209 * XXX How does private space interact with PCI-PCI bridges? 210 */ 211 if (ps->ps_b == pbus || ps->ps_b == sbus) { 212 if (ps->ps_d > (31 - 11)) 213 return (1); 214 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) | 215 offset; 216 } else { 217 /* The tag is already in the correct format. */ 218 ps->ps_addr_val = tag | offset | 1; 219 } 220 221 return (0); 222 } 223 224 pcireg_t 225 i80312_pci_conf_read(void *v, pcitag_t tag, int offset) 226 { 227 struct i80312_softc *sc = v; 228 struct pciconf_state ps; 229 vaddr_t va; 230 pcireg_t rv; 231 u_int s; 232 233 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 234 return ((pcireg_t) -1); 235 236 PCI_CONF_LOCK(s); 237 238 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 239 ps.ps_addr_val); 240 241 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 242 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) { 243 /* 244 * Clear the Master Abort by reading the PCI 245 * Status Register. 246 */ 247 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 248 ps.ps_csr_reg); 249 #if 0 250 printf("conf_read: %d/%d/%d bad address\n", 251 ps.ps_b, ps.ps_d, ps.ps_f); 252 #endif 253 rv = (pcireg_t) -1; 254 } 255 256 PCI_CONF_UNLOCK(s); 257 258 return (rv); 259 } 260 261 void 262 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 263 { 264 struct i80312_softc *sc = v; 265 struct pciconf_state ps; 266 u_int s; 267 268 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 269 return; 270 271 PCI_CONF_LOCK(s); 272 273 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 274 ps.ps_addr_val); 275 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val); 276 277 PCI_CONF_UNLOCK(s); 278 } 279